Preliminary experiments for power supply noise reduction using stubs

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Volumn , Issue , 2004, Pages 286-289

  Nakura, Toru ^a   Ikeda, Makoto ^a   Asada, Kunihiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COUPLED CIRCUITS; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; LSI CIRCUITS; NOTCH FILTERS; TERMINALS (ELECTRIC); TRANSISTORS;

OFF-CHIP DECOUPLING CAPACITOR; OPERATING FREQUENCY; POWER SUPPLY NOISE REDUCTION; STUBS;

NOISE ABATEMENT;

EID: 14544271032     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Mustafa Badaroglu, Kris Tiri, Stephane Donnay, Piet Wambacq, Ingrid Verbauwhede, Georges Gielen, Hugo De Man, "Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients," in 39th Design Automation Conf., June 2002, pp.399-404.
2. K. Y. Chen, William D. Brown, Leonard W. Schaper, Simon S. Ang, Hameed A. Naseem, "A Study of the High Frequency Performance of Thin Film Capacitors for Electronic Packaging," IEEE Trans. Advanced Packag., May 2000, pp.293-302.
3. Toru Nakura, Makoto Ikeda, Kunihiro Asada, "Theoretical Study of Stubs for Power Line Noise Reduction," in IEEE Custom Integrated Circuits Conference (CICC), Sec.31-4, Sept. 2003.
4. "International Technology Roadmap for Semiconductors 2002 Update," [Online] Available: http://public.itrs.net/