Scaling Trends of On-Chip Power Distribution Noise

International Workshop on System Level Interconnect Prediction

Volumn , Issue , 2002, Pages 47-53

  Mezhiba, Andrey V ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

Power distribution; Power supply noise; Technology scaling

Indexed keywords

CURRENT DENSITY; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; FLIP CHIP DEVICES; INTEGRATED CIRCUITS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

GROUND DISTRIBUTION NETWORKS; POWER SUPPLY NOISE; TECHNOLOGY SCALING; VOLTAGE DROPS;

MICROPROCESSOR CHIPS;

EID: 1442357956     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505358.505359     Document Type: Conference Paper

References (19)

1. Semiconductor Industry Association, "International Technology Roadmap for Semiconductors, 2001 Update," http://public.itrs.net, 2001.
2. M. Benoit and S. Taylor and D. Overhauser and S. Rochel, "Power Distribution in High-Performance Design," Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 274-278, August, 1998.
3. L. C. Tsai, "A 1 GHz PA-RISC Processor," Proceedings of the IEEE International Solid-State Circuits Conference, pp. 322-323, February, 2001.
4. C. J. Anderson and others, "Physical Design of a Fourth-Generation POWER GHz Microprocessor," Proceedings of the IEEE International Solid-State Circuits Conference, pp. 232-233, February, 2001.
5. R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Ride-out, E. Bassous, and A. R. LeBlanc, "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," IEEE Journal of Solid-State Circuits, Vol. SC-33, No. 5, pp. 256-268, October, 1974.
6. K. C. Saraswat and E. Mohammadi, "Effect of scaling of interconnections on the time delay of VLSI circuits," IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, pp. 645-650, April, 1982.
7. W. S. Song and L. A. Glasser, "Power Distribution Techniques for VLSI Circuits," IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 1, pp. 150-156, February, 1986.
8. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990.
9. P. Larsson, "di/dt Noise in CMOS Integrated Circuits," Analog Integrated Circuits and Signal Processing, Vol. 14, No. 1/2, pp. 113-129, September, 1997.
10. L. A. Arledge Jr. and W. T. Lynch, "Scaling and Performance Implications for Power Supply and Other Signal Routing Constraints Imposed by I/O Limitations," Proceedings of the IEEE Symposium on IC/Package Design Integration, pp. 45-50, February, 1998.
11. G. A. Katopis, "Delta-I Noise Specification for a High-Performance Computing Machine," Proceedings of the IEEE, Vol. 73, No. 9, pp. 1405-1415, September, 1985.
12. B. D. McCredie and W. D. Becker, "Modeling, Measurement, and Simulation of Simultaneous Switching Noise," IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B, Vol. 19, No. 3, pp. 461-472, August, 1996.
13. R. R. Tummala and E. J. Rymaszewski and A. G. Klopfenstein, Microelectronics Packaging Handbook, Chapman & Hall, New York, 1997.
14. D. Sylvester and H. Kaul, "Future Performance Challenges in Nanometer Design," Proceedings of the IEEE/ACM Design Automation Conference, pp. 3-8, June, 2001.
15. A. V. Mezhiba and E. G. Friedman, "Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits," Proceedings of the IEEE International Symposium on Quality Electronic Design, March, 2002.
16. A. V. Mezhiba and E. G. Friedman, "Inductance/Area/-Resistance Tradeoffs in High Performance Power Distribution Grids," Proceedings of the IEEE International Symposium on Circuits and Systems, May, 2002.
17. I. S. Kourtev and E. G. Friedman, Timing Optimization Through Clock Skew Scheduling, Kluwer Academic Publishers, Norwell, Massachusetts, 2000.
18. A. Deutsch et al., "The Importance of Inductance and Inductive Coupling for On-Chip Wiring," Proceedings of the Topical Meeting on Electrical Performance of Electrical Packaging, pp. 53-56, October, 1997.
19. Y. I. Ismail and E. G. Friedman, On-Chip Inductance in High Speed Integrated Circuits, Kluwer Academic Publishers, Norwell, Massachusetts, 2001.