Technology Trends in Power-Grid-Induced Noise

International Workshop on System Level Interconnect Prediction

Volumn , Issue , 2002, Pages 55-59

  Nassif, Sani R ^a   Fakhouri, Onsi ^b  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Power grid noise

Indexed keywords

APPROXIMATION THEORY; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ITERATIVE METHODS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICES; SPURIOUS SIGNAL NOISE;

GROUND NETS; POWER GRID NOISE;

ELECTRIC POWER SYSTEMS;

EID: 1442309106     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505358.505360     Document Type: Conference Paper

References (6)

1. G. Bai and B. Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. In Proc. Design Automation Conference, pages 295-300, Las Vegas, NV, June 2001.
2. K. Gala, V. Zolotov, R. Panda, B. Young, J. Wang, and D. Blaauw. On chip inductance modeling and analysis. In Proc. Design Automation Conference, Los Angeles, CA, June 2000.
3. V. Mehrotra, S. Nassif, D. Boning, and J. Chung. Modeling the effects of manufacturing variations on high-speed microprocessor interconnect performance. In Proceedings of IEDM, 1998.
4. S. R. Nassif and J. N. Kozhaya. Fast Power Grid Simulation. In Proc. Design Automation Conference, pages 156-161, Los Angeles, CA, June 2000.
5. Semiconductor Industry Association, http://public.itrs.net/Files/1999_SIA_Roadmap. The International Technology Roadmap for Semiconductors, 1999.
6. H. Su, S. Sapatnaker, and S. Nassif. An algorithm for optimal decoupling capacitor sizing and placement. In Proc. Internations Symposim on Physical Design, 2002.