Loop scheduling for multithreaded processors

International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

Volumn , Issue , 2004, Pages 361-366

  Dimitriou, Georgios ^a   Polychronopoulos, Constantine ^b  

^a UNIVERSITY OF THESSALY   (Greece)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOOP ITERATION; LOOP SCHEDULING; MULTITHREADED PROCESSORS; WELL-BALANCED TASKS;

BENCHMARKING; BUFFER STORAGE; COMPETITION; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ITERATED SWITCHING NETWORKS; SCHEDULING; SIMULATORS; SWITCHING SYSTEMS; SYNCHRONIZATION;

PROCESS ENGINEERING;

EID: 13944271861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. D.A. Padua, D.J. Kuck, and D.H. Lawrie, "High-speed Multiprocessors and Compilation Techniques", IEEE Trans. on Computers, C-29(9), 1980, pp. 763-776.
2. D.A. Padua, and M.J. Wolfe, "Advanced Compiler Optimizations for Supercomputers", Communications of the ACM, 29(12), 1986, pp. 1184-1201.
3. U. Banerjee, Dependence Analysis for Supercomputing, Kluwer Academic Publishers, Boston, 1988.
4. B.R. Rau, and J.A. Fisher, "Instruction-level Parallel Processing: History, Overview and Perspectives", Journal of Supercomputing, 7(1), 1993, pp. 9-50.
5. D.M. Lavery, Modulo Scheduling for Control-Intensive General Purpose Programs, PhD dissertation, University of Illinois at Urbana-Champaign, 1997.
6. W.W. Hwu, S.A. Mahlke, W.Y. Chen, et al., "The Superblock: An Effective Technique for VLIW and Superscalar Compilation", Journal of Supercomputing, 7, 1993, pp. 229-248.
7. B.J. Smith, "A Pipelined, Shared Resource MIMD Computer", Int. Conf. on Parallel Processing, 1978, pp. 6-8.
8. J.P. Laudon, Architectural and Implementation Tradeoffs for Multiple-Context Processors, PhD dissertation, Stanford University, 1994.
9. D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism", Int. Symp. on Computer Architecture, 1995, pp. 392-403.
10. G.S. Sohi, S.E. Breach, and T.N. Vijaykumar, "Multiscalar Processors", Int. Symp. on Comp. Arch.., 1995, pp. 414-425.
11. J. Tsai, and P. Yew, "The Superthreaded Architecture: Thread Pipelining with Run-time Data Dependence Checking and Control Speculation", Conf. on Parallel Architectures and Compilation Techniques, 1996, pp. 35-46.
12. V.S. Krishnan, and J. Torrellas, "A Clustered Approach to Multithreaded Processors", Int Parallel Processing Symp., 1998.
13. P. Marcuello, A. Gonzalez, and J. Tubella, "Speculative Multithreaded Processors", Int. Conf. on Supercomputing, 1998, pp. 77-84.
14. H. Akkary, and M.A. Driscoll, "A Dynamic Multithreading Processor", Int. Symp. on Microarchitecture, 1998, pp. 226-236.
15. P.K. Dubey, K. O'Brien, K.M. O'Brien, and C. Barton, Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading, Res. Rep. RC 19928, IBM T. J. Watson Research Center, 1995.
16. M. Prvulovic, M.J. Garzaran, L. Rauchwerger, and J. Torrellas, "Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization", Int. Symp. on Computer Architecture, 2001.
17. A. Zhai, C.B. Colohan, J.G. Steffan, and T.C. Mowry, "Compiler Optimization of Scalar Value Communication between Speculative Threads", Int. Conf. on Arch. Support for Programming Languages and Operating Systems, 2002.
18. M.B. Girkar, Functional Parallelism: Theoretical Foundations and Implementations, PhD dissertation, University of Illinois at Urbana-Champaign, 1992.
19. C.D. Polychronopoulos, α-Coral: A New Multithreaded Processor Architecture, its Compiler Support, and Simulation of a multi-α-Coral Parallel System, Project Proposal, CSRD, University of Illinois at Urbana-Champaign, 1997.
20. G. Dimitriou, Loop Scheduling for Multithreaded Processors, PhD dissertation, University of Illinois at Urbana-Champaign, 2000.
21. C. Moura, SuperDLX - A Generic Superscalar Simulator, ACAPS Tech. Memo 64, School of Computer Science, McGill University, 1993.