CASSE: A system-level modeling and design-space exploration tool for multiprocessor systems-on-chip

Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Volumn , Issue , 2004, Pages 476-483

  Reyes, Victor ^a   Bautista, Tomás ^a   Marrero, Gustavo ^a   Carballo, Pedro P ^a   Kruijtzer, Wido ^b  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

AMBIENT INTELLIGENCE; ARCHITECTURAL MODELING; IMAGING APPLICATIONS; SYSTEMS-ON-CHIP (SOC);

ABSTRACTING; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ENCODING (SYMBOLS); IMAGING TECHNIQUES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS; VIDEO SIGNAL PROCESSING;

MULTIPROCESSING SYSTEMS;

EID: 13944255798     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2004.1333313     Document Type: Conference Paper

References (19)

1. CAMELLIA webpage: www.iuma.ulpgc.es/camellia/
2. K. Keutzer, S. Malik, R. Newton, J. Rabaey and S. Sangiovanni-Vicentelli, "System Level Design: Orthogonalization of Concerns and Platform-Based Design", in Proc. IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 19, No. 12, December 2000
3. B. Kienhuis, E. Deprettere, K. Vissers and P. van der Wolf, "An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures", in Proc. 11-th Int. Conf. on Application-specific Systems, Architectures and Processors, Zurich, Switzerland, July 14-16 1997
4. J.A. Rowson and A. Sangiovanni-Vicentelli, "Interface-Based Design", in Proc. Of Design Automation Conference, Anaheim, California, June 1997
5. Lukai Cai and Daniel Gajski, "Transaction Level Modeling: An Overview", in CODES+ISSS'03, California, USA, October 2003
6. W. Cesario, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A.A. Jerraya, L. Gauthier and M. Diaz-Nava, "Multiprocessor SoC Platforms: A Component-Based Design Approach", in IEEE Design & Test of Computers, December 2002
7. M-A. Dziri, W. Cesario, F. Wagner, and A.A. Jerraya, "Unified Component Integration Flow for Multi-Processor SoC Design and Validation", in Proc. DATE'04, Paris, February 2004
8. T. Kogel, A. Wieferink, R. Leupers, G. Ascheid, H. Meyr, D. Bussaglia, M. Ariyamparambath, "Virtual Architecture Mapping: A SystemC based Methodology for Architectural Exploration of System-on-Chip Designs", in Int. Workshop on Systems, Architecture, Modeling and Simulation, samos, Greece, July 2003
9. P. Lieverse, T. Stefanov, P. van der Wolf, E. Deprettere, "System Level Design with Spade: and M-JPEG Case Study", in Proc. ICCAD'2001, November 2001, San Jose, CA
10. A. Nieuwland, J. Kang, O.P. Gangwal, R. Sethuraman, N. Busa, K. Goossens, R. Peset Llopis, and Paul Lippens, "C-HEAP: A Heterogeneous Multi-processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems", in Design automation for Embedded Systems, Vol 7(3): 229-266, 2002, Kluwer
11. M.J. Rutten, J.T.J. van Eijndhoven, and E.-J.D. Pol, "Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing", in Workshop on Parallel and Distributed Computing in Image Processing, Video Processing, and Multimedia (PDIVM'2002), Fort Lauderdale, USA, 2002, pp. 39-50
12. T. Stefanov, P. Lieverse, E. Deprettere, P. van der Wolf, "Y-Chart Based System Level Performance Analysis: An M-JPEG Case Study", in Proc. of the Progress Workshop, 2000
13. Functional Specification for SystemC 2.0.1, April 2002, http://www.systemc.org
14. SystemC 2.0.1 Language Reference Manual
15. Open Core Protocol Specification-v1.0. http://www.sonic.com. October 1999
16. Virtual Component Interface Standard Version 2. On-Chip Bus DWG (OCB 2.2.0), http://www.vsi.org, April 2001
17. ARM. AMBA AXI Protocol Specification, June 2003
18. Harwig, Rick and Emile Aarts, "Ambient Intelligence: Invisible Electronics Emerging", in Proc. of the 2002 International Interconnect Technology Conference, San Francisco, pp. 3-5
19. P. Klapproth, "Architectural Concept for IP re-use", in VLSI ASP DAC, December 2002