Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAM

IEEE Electron Device Letters

Volumn 26, Issue 2, 2005, Pages 66-68

  Wu, Yung Hsien ^a   Hsieh, Eugine ^a   Kuo, Robert ^a   Lai, Sierra ^a   Ku, Alex ^a  

^a ProMOS Technologies Inc   (Taiwan)

Author keywords

N 2O reoxidation; Reoxidation of nitride oxide; Storage dielectric; Trench dynamic random access memory (DRAM)

Indexed keywords

REOXIDATION; STORAGE DIELECTRIC; TRENCH DYNAMIC RANDOM ACCESS MEMORY (DRAM); TUNNELING LEAKAGE CURRENT;

AMMONIA; CAPACITANCE; CAPACITORS; DIELECTRIC MATERIALS; ELECTRIC PROPERTIES; ELECTRON TRAPS; LEAKAGE CURRENTS; NITRIDING; NITROGEN OXIDES; OXIDATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 13444280432     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.841189     Document Type: Article

References (13)

1. S. Saida, T. Sato, M. Sato, and M. Kito, "Embedded trench DRAM's for sub-0.1μm generation by using hemispherical-grain technique and LOCOS collar process," IEEE Trans. Semiconduct. Manufact., vol. 14, no. 3, pp. 196-201, Aug. 2001.
2. J. Lutzen, A. Birner, M. Goldbach, M. Gutsche, T. Hecht, S. Jakschik, A. Orth, A. Sanger, U. Schroder, H. Seidl, B. Sell, and D. Schumann, "Integration of capacitor for sub-100-nm DRAM trench technology," in Symp. VLSI Tech. Dig., 2002, pp. 178-179.
3. M. Gutsche, H. Seidl, J. Luetzen, A. Birner, T. Hecht, S. Jakschik, M. Kerber, M. Leonhardt, P. Moll, T. Pompl, H. Reisinger, S. Rongen, A. Saenger, U. Schroeder, B. Sell, A. Wahl, and D. Schumann, " Capacitance enhancement techniques for sub-100 nm trench DRAMs," in IEDM Tech. Dig., 2001, pp. 411-414.
4. 3-nitrided oxide as gate dielectric for nMOS transistors," IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1907-1913, Nov. 1996.
5. H. S. Momose, T. Morimoto, Y. Ozawa, M. Tsuchiaki, M. Ono, K. Yamabe, and H. Iwai, "Very lightly nitrided oxide gate MOSFETs for deep-sub-micron CMOS devices," in IEDM Tech. Dig., 1991, pp. 359-362.
6. 2O ambient," Electron. Lett., vol. 31, pp. 1196-1198, Jul. 1995.
7. H. Fukuda, A. Uchiyama, T. Kuramochi, T. Hayashi, T. Iwabuchi, T. Ono, and T. Takayashiki, "High-performance scaled flash-type EEPROMs with heavily oxynitrided tunnel oxide films," in IEDM Tech. Dig., 1992, pp. 465-468.
8. K. P. Muller, B. Flietner, C. L. Hwang, R. L. Kleinhenz, T. Nakao, R. Ranade, Y. Tsunashima, and T. Mii, "Trench storage node technology for gigabit DRAM generations," in IEDM Tech. Dig., 1996, pp. 507-510.
9. A. Philipossian and D. B. Jackson, "Kinetics of oxide growth during reoxidation of lightly nitrided oxides," J. Electrochem. Soc., vol. 139, no. 9, pp. L82-L83, 1992.
10. E. Wu, C. Hwang, R. Vollertsen, H. Shen, R. Kleinhenz, C. Radens, and A. Strong, "Thickness and polarity dependence of intrinsic breakdown of ultra-thin reoxidized-nitride for DRAM technology applications," in IEDM Tech. Dig., 1997, pp. 77-80.
11. 2," J. Appl. Phys., vol. 63, no. 3, pp. 797-802, 1988.
12. S. Fleischer, P. T. Lai, and Y. C. Cheng, "Simplified closed-form trapassisted tunneling model applied to nitrided oxide dielectric capacitors," J. Appl. Phys., vol. 72, no. 12, pp. 5711-5715, 1992.
13. J. Lee, G. Bosman, K. R. Green, and D. Ladwig, "Model and analysis of gate leakage current in ultrathin nitrided oxide MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 7, pp. 1232-1241, Jul. 2002.