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Volumn 14, Issue 1, 2004, Pages 28-30

43 Gb/s Decision Circuits in InP DHBT Technology

Author keywords

Flip flops; Frequency divider; HBT; High speed integrated circuits; InP; Retimer

Indexed keywords

BANDWIDTH; BINARY SEQUENCES; BIT ERROR RATE; CAPACITANCE; CAPACITORS; CURRENT DENSITY; DEMULTIPLEXING; ELECTRIC LINES; ELECTRIC POTENTIAL; EMITTER COUPLED LOGIC CIRCUITS; FLIP FLOP CIRCUITS; FREQUENCY DIVIDING CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; HIGH ELECTRON MOBILITY TRANSISTORS; INTEGRATED CIRCUITS; SEMICONDUCTING INDIUM PHOSPHIDE;

EID: 1342329456     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2003.821504     Document Type: Article
Times cited : (6)

References (11)
  • 2
    • 0030125125 scopus 로고    scopus 로고
    • 46 Gb/s DEMUX, 50 Gb/s MUX. and static frequency divider in silicon bipolar technology
    • Apr.
    • A. Felder, M. Moller, J. Popp, J. Bock, and H.-M. Rein, "46 Gb/s DEMUX, 50 Gb/s MUX. and static frequency divider in silicon bipolar technology," IEEE J. Solid-State Circuits, vol. 31, pp. 481-486. Apr. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , pp. 481-486
    • Felder, A.1    Moller, M.2    Popp, J.3    Bock, J.4    Rein, H.-M.5
  • 5
    • 0000036195 scopus 로고    scopus 로고
    • Si and SiGe bipolar ICs for 10 to 40 Gb/s optical-fiber TDM links
    • June
    • H.-M. Rein, "Si and SiGe bipolar ICs for 10 to 40 Gb/s optical-fiber TDM links," Int. J. High Speed Electron. Syst., vol. 9, no. 2. pp. 347-383, June 1998.
    • (1998) Int. J. High Speed Electron. Syst. , vol.9 , Issue.2 , pp. 347-383
    • Rein, H.-M.1
  • 9
    • 0037068729 scopus 로고    scopus 로고
    • 48 Gbit/s InP DHBT MS-FF with very low time jitter
    • Sept.
    • A. Konczykowska, F. Jorge, A. Kasbari, N. Sahri, and J. Godin, "48 Gbit/s InP DHBT MS-FF with very low time jitter," Electron. Lett., vol. 38, no. 19, pp. 1081-1083, Sept. 2002.
    • (2002) Electron. Lett. , vol.38 , Issue.19 , pp. 1081-1083
    • Konczykowska, A.1    Jorge, F.2    Kasbari, A.3    Sahri, N.4    Godin, J.5
  • 10
    • 0037030552 scopus 로고    scopus 로고
    • High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs
    • June
    • K. Ishii, H. Nosaka, M. Ida, K. Kurishima, I. Enoki, T. Shibata, and E. Sano, "High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs," Electron. Lett., vol. 38, no. 12, pp. 557-558, June 2002.
    • (2002) Electron. Lett. , vol.38 , Issue.12 , pp. 557-558
    • Ishii, K.1    Nosaka, H.2    Ida, M.3    Kurishima, K.4    Enoki, I.5    Shibata, T.6    Sano, E.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.