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Volumn 2002-January, Issue , 2002, Pages 163-172
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Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip
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Author keywords
Reduced instruction set computing
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Indexed keywords
BANDWIDTH;
COMPUTATION THEORY;
DATA HANDLING;
DYNAMIC RANDOM ACCESS STORAGE;
INTEGRATED CIRCUIT DESIGN;
MATRIX ALGEBRA;
MEMORY ARCHITECTURE;
MICROPROCESSOR CHIPS;
REDUCED INSTRUCTION SET COMPUTING;
BANDWIDTH LIMITEDS;
BUILDING A PROTOTYPES;
DATA-INTENSIVE ARCHITECTURE SYSTEMS;
DESIGN AND IMPLEMENTATIONS;
HIGH PERFORMANCE PROCESSORS;
MULTIMEDIA APPLICATIONS;
PROCESSING-IN-MEMORY CHIPS;
SPARSE MATRIX COMPUTATIONS;
COMPUTER ARCHITECTURE;
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EID: 12444317990
PISSN: 10636862
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ASAP.2002.1030716 Document Type: Conference Paper |
Times cited : (17)
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References (14)
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