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Volumn 2002-January, Issue , 2002, Pages 163-172

Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip

Author keywords

Reduced instruction set computing

Indexed keywords

BANDWIDTH; COMPUTATION THEORY; DATA HANDLING; DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT DESIGN; MATRIX ALGEBRA; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING;

EID: 12444317990     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2002.1030716     Document Type: Conference Paper
Times cited : (17)

References (14)
  • 1
    • 84948803347 scopus 로고    scopus 로고
    • http://www.altivec.org.
  • 5
    • 2442494905 scopus 로고    scopus 로고
    • The Architecture of the DIVA Processing-in-Memory Chip
    • June
    • J. Draper, et al, "The Architecture of the DIVA Processing-in-Memory Chip", to appear at the International Conference on Supercomputing, June 2002.
    • (2002) International Conference on Supercomputing
    • Draper, J.1
  • 6
    • 0005698063 scopus 로고    scopus 로고
    • Mapping Irregular Application to DIVA, a PIM-based Data-Intensive Architecture
    • November
    • Mary Hall, et al, "Mapping Irregular Application to DIVA, a PIM-based Data-Intensive Architecture," Supercomputing, November 1999.
    • (1999) Supercomputing
    • Hall, M.1
  • 9
    • 0033115361 scopus 로고    scopus 로고
    • Embedded DRAM technology
    • April
    • S. Iyer and H. Kalter, "Embedded DRAM technology," IEEE Spectrum, April 1999, pp. 56-64.
    • (1999) IEEE Spectrum , pp. 56-64
    • Iyer, S.1    Kalter, H.2
  • 10
    • 84948803348 scopus 로고    scopus 로고
    • http://www.jedec.org.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.