Optimum and heuristic synthesis of multiple word-length architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 1, 2005, Pages 39-57

  Constantinides, George A ^a   Cheung, Peter Y K ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

Binding; Bitwidth; Digital signal processing; Field programmable gate array; High level synthesis; Scheduling; Word length

Indexed keywords

ADAPTIVE FILTERING; ALGORITHMS; BENCHMARKING; COMPUTATIONAL COMPLEXITY; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; FUNCTIONS; GRAPH THEORY; INTEGER PROGRAMMING; LEAST SQUARES APPROXIMATIONS; POLYNOMIALS; PROBLEM SOLVING; RESOURCE ALLOCATION; SCHEDULING;

BITWIDTH; HIGH-LEVEL SYNTHESIS; RESOURCE BINDING; WORD-LENGTH;

COMPUTER ARCHITECTURE;

EID: 13144282745     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.840398     Document Type: Article

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