A Single Event Latchup Suppression Technique for COTS CMOS ICs

IEEE Transactions on Nuclear Science

Volumn 50, Issue 6 I, 2003, Pages 2219-2224

  Spratt, James P ^a   Pickel, James C ^a,b   Leadon, Roland E ^a   Lacoe, Ronald C ^c   Moss, Steven C ^c   LaLumondiere, Stephen D ^c  

^a Full Circle Research Inc ^*  (United States)

^b PR and T Inc   (United States)

^c AEROSPACE CORPORATION   (United States)

Author keywords

COTS CMOS integrated circuits; Displacement damage to suppress latchup; Single event latchup suppression

Indexed keywords

BIPOLAR TRANSISTORS; COSTS; CYCLOTRONS; FLIP FLOP CIRCUITS; HEAVY IONS; ION IMPLANTATION; IRRADIATION; SILICON;

COMMERCIAL OFF-THE-SHELF (COTS) CMOS INTEGRATED CIRCUITS; DISPLACEMENT DAMAGE TO SUPPRESS LATCHUP; SINGLE EVENT LATCHUP SUPPRESSION;

CMOS INTEGRATED CIRCUITS;

EID: 1242287908     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2003.821607     Document Type: Conference Paper

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