Bus-switch coding for reducing power dissipation in off-chip buses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 12, 2004, Pages 1374-1377

  Olivieri, Mauro ^a,b   Pappalardo, Francesco ^a,b   Visalli, Giuseppe ^a,b  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

Bus Transfer; Encoding; Power demand; Very large scale integraton (VLSI)

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC BATTERIES; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); PROBLEM SOLVING; SWITCHING; VLSI CIRCUITS;

BUS TRANSFER; CLUSTERED BUS INVERT (CBI) CODING; POWER DEMAND; POWER DISSIPATION;

ELECTRIC LOSSES;

EID: 12344303316     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.837998     Document Type: Article

References (14)

1. L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi, "Architectures and synthesis algorithms for power-efficient bus interfaces," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1498-1506, Sept. 2000.
2. A. Chandrakasan and R. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, pp. 498-523, Apr. 1995.
3. T. Kam, S. Rawat, D. Kirkpatrick, R. Roy, G. S. Spirakis, N. Sherwani, and C. Peterson, "EDA challenges facing future microprocessor design, " IEEE Trans. Computer-Aided Design, vol 19, pp. 1498-1506, Dec. 2000.
4. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Information-theoretic bounds on average signal transition activity," IEEE Trans. VLSI Syst., vol. 7, pp. 359-368, Sept. 1999.
5. R. Siegmund, C. Kretzschmar, and D. Muller, "Adaptive bus encoding technique for switching activity reduced data transfer over wide system buses," in Int. Workshop Power and Timing Modeling Optimization Simulation, Göttingen, Germany, 2000.
6. M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. VLSI Syst., vol. 3, pp. 49-58, Mar. 1995.
7. P. P. Sotiriadis and A. Chandrakasan, "Bus energy minimization by Transition Pattern Coding (TPC) in deep sub-micron technologies," in Proc. IEEE Int. Conf. CAD, San Jose, CA, 2000, pp. 322-327.
8. P. P. Sotiriadis, T. Konstantakopoulos, and A. Chandrakasan, "Analysis and implementation of charge recycling for deep sub-micron buses," in Int. Symp. Low-Power Electronics Design, Huntington Beach, CA, Aug. 2001.
9. P. P. Sotiriadis and A. Chandrakasan, "Low power bus coding techniques considering interwire capacitances," in IEEE Custom Integrated Circuits Conf., May 2000, pp. 507-510.
10. STMicroelectronics, Corelib HCMOS8 DataBook and CB35000 Standard Cell Library Datasheet, 2001.
11. STMicroelectronics, Corelib HCMOS9 DataBook and CB45000 Standard Cell Library Datasheet, Aug. 2002.
12. K. L. Tai, "System-In-Package (SIP): Challenges and opportunities," in Proc. IEEE ASP-DAC, Jan. 2000, pp. 191-196.
13. Y. Zhang, J. Lach, K. Skadron, and M. R. Stan, "Odd/even bus invert with two-phase transfer for buses with coupling," in Int. Symp. Low-Power Electronics and Design, Monterey, CA, Aug. 2002.
14. H. Zhang, V. George, and J. M. Rabaey, "Low-swing on-chip signling techniques: effectiveness and robustness," IEEE Trans. VLSI Syst., vol. 8, pp. 264-272, June 2000.