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Volumn 48, Issue 4, 2001, Pages 394-399
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A low-voltage sample-and-hold circuit in-standard CMOS technology operating at 40 Ms/s
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Author keywords
Low voltage; Sample and hold; Switched capacitor circuits
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Indexed keywords
CAPACITORS;
ELECTRIC CONDUCTANCE;
ELECTRIC POWER SUPPLIES TO APPARATUS;
FREQUENCIES;
HARMONIC DISTORTION;
MOS DEVICES;
OPERATIONAL AMPLIFIERS;
THRESHOLD VOLTAGE;
SAMPLE-AND-HOLD CIRCUIT;
SWITCHED-CAPACITOR CIRCUIT;
SWITCHED-OP-AMP TECHNIQUE;
TOTAL HARMONIC DISTORTION;
CMOS INTEGRATED CIRCUITS;
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EID: 0035300333
PISSN: 10577130
EISSN: None
Source Type: Journal
DOI: 10.1109/82.933801 Document Type: Article |
Times cited : (40)
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References (15)
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