Low-temperature dopant activation technology using elevated Ge-S/D structure

Applied Surface Science

Volumn 224, Issue 1-4, 2004, Pages 73-76

  Takeuchi, Hideki ^a   Ranade, Pushkar ^a,b   King, Tsu Jae ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Dept of Mat Sci and Engineering ^*

Author keywords

CMOS; Elevated S D; Ge; Shallow junction

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; CRYSTALLIZATION; DIFFUSION; DOPING (ADDITIVES); INTERFACES (MATERIALS); LOW TEMPERATURE EFFECTS; MOSFET DEVICES; PERMITTIVITY; POLYCRYSTALLINE MATERIALS; SILICON;

ELEVATED S/D; SHALLOW JUNCTION; SOLID PHASE CRYSTALLIZATION;

GERMANIUM;

EID: 1142268149     PISSN: 01694332     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.apsusc.2003.08.094     Document Type: Conference Paper

References (8)

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3. Ranade P., Takeuchi H., Subramanian V., King T.-J. IEEE Elect. Dev. Lett. 23:2002;218.
4. Ranade P., Takeuchi H., Lee W.-C., Subramanian V., King T.-J. IEEE Trans. Elect. Dev. 49:2002;1436.
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7. Takeuchi H., Ranade P., Subramanian V., King T.-J. Appl. Phys. Lett. 80:2002;3706.
8. Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor, C. Hu, 58th Device Research Conference, Digest of Technical Papers, 2000, p. 23.