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Volumn 1, Issue , 2003, Pages 128-131

Two-dimensional common-centroid stack generation algorithms for analog VLSI

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG VLSI; COMMON CENTROID; EULERIAN; EULERIAN GRAPHS; GENERATION ALGORITHM;

EID: 11244330397     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277506     Document Type: Conference Paper
Times cited : (5)

References (10)
  • 1
    • 0026118974 scopus 로고
    • Koan/Anagram II: New tools for device-level analog placement and routing
    • n. March
    • J. M. Colin, D. J. Garrod, R. A. Rutenbar and L R Carley, "KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing", IEEE Journal of Solid State Circuits, vol. 26, n. 3, pp. 330-342, March 1991.
    • (1991) IEEE Journal of Solid State Circuits , vol.26 , Issue.3 , pp. 330-342
    • Colin, J.M.1    Garrod, D.J.2    Rutenbar, R.A.3    Carley, L.R.4
  • 3
    • 0029220994 scopus 로고
    • Optimum CMOS stack generation with analog constraints
    • Jan
    • E. Malavasi and D. Pandini, "Optimum CMOS stack generation with analog constraints," IEEE Trans. Computer-AidedDesign, vol. 14. pp. 107-122. Jan. 1995.
    • (1995) IEEE Trans. Computer-AidedDesign , vol.14 , pp. 107-122
    • Malavasi, E.1    Pandini, D.2
  • 5
    • 0029697870 scopus 로고    scopus 로고
    • An 0(n) algorithm for transistor stacking with performance constraints
    • June
    • A. Basaran and R. A. Rutenbar, "An 0(n) algorithm for transistor stacking with performance constraints", in Proc. Of IEEE/ACM DAC, pp. 221-226. June 1996.
    • (1996) Proc. Of IEEE/ACM DAC , pp. 221-226
    • Basaran, A.1    Rutenbar, R.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.