Parasitic-aware synthesis of RF LNA circuits considering quasi-static extraction of inductors and interconnects

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Bhaduri, Amitava ^a   Vijay, Vikas ^a   Agarwal, Anuradha ^a   Vemuri, Ranga ^a   Mukherjee, Bhaskar ^b   Wang, Peiyan ^b   Pacelli, Andrea ^b  

^a UNIVERSITY OF CINCINNATI   (United States)

^b STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION; SIMULATED ANNEALING;

CAPACITIVE PARASITICS; NOISE FIGURE (NF); ON-CHIP INDUCTORS;

INTEGRATED CIRCUIT LAYOUT;

EID: 11144248881     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. T. H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 2002.
2. X. Yang, T. Wu and J. McMacken. "Design of LNA at 2.4 GHz Using 0. 25 um Technology". In Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pages 12-17, Sept. 2001.
3. C. De Ranter et al. "CYCLONE: Automated Design and Layout of RF LC-Oscillators". In DAC, pages 11-14, June 2000.
4. M. del Mar Hershenson et al. "Design and optimization of LC oscillators". In International Conference on Computer-Aided Design, 1999.
5. P. Vancorenland, G. Van der Plas, M. Steyaert, G. Gielen and W. Sansen. "A Layout-aware Synthesis Methodology for RF Circuits". In International Conference on Computer-Aided Design, 2001.
6. R. Gupta, B. M. Ballweber and D. J. Allstot. "Design and Optimization of CMOS RF Power Amplifiers". In IEEE Journal of Solid-State Circuits, pages 166-175, 2001.
7. D. K. Shaeffer and T. H. Lee. "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier". In IEEE Journal of Solid-State Circuits, pages 745-759, May 1997.
8. H. Sampath and R. Vemuri. "MSL: A High-Level Language for Parameterized Analog and Mixed-Signal Layout Generators". In Proc. of IFIP 12th International Conf. on VLSI, 2003.
9. A. Pacelli. "A local circuit topology for inductive parasitics". In ICCAD, pages 208-214, Nov. 2002.
10. A. E. Ruehli and A. C. Cangellaris. "Progress in the Methodologies for the Electrical Modeling of Interconnects and Electronic Packages". In Proceedings of the IEEE, pages 740-771, May 2001.
11. M. Kamon, M. Tsuk and J. White. "FASTHENRY: A multipole-accelerated 3-D inductance extraction program". In IEEE Transactions on Microwave Theory and Techniques, pages 1750-1758, Sept. 1994.
12. H. M. Greenhouse. "Design of Planar Rectangular Microelectronic Inductors". In IEEE Trans. Parts, Hybrids and Packaging, pages 101-109. Jun 1974.