Design of LNA at 2.4 GHz using 0.25 μm technology

2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2001

Volumn , Issue , 2001, Pages 12-17

  Xiaomin, Yang ^a   Wu, T ^a   McMacken, J ^b  

^a University of Central Florida   (United States)

^b Agere System Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; LOW NOISE AMPLIFIERS;

CMOS LOW NOISE AMPLIFIERS; CMOS PROCESSS; DESIGN PROCEDURE; DIFFERENTIAL LNA; FULLY INTEGRATED; OFF-CHIP COMPONENTS; SINGLE-ENDED; THIRD-ORDER INPUT INTERCEPT POINTS;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 84952043684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMIC.2001.942333     Document Type: Conference Paper

References (13)

1. T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge, U.K.: Cambridge University Press, 1998
2. D. K. Shaeffer and T. H. Lee, The Design and Implementation of Low-Power CMOS Radio Receivers, Kluwer academic publishers, 1999
3. Y. Ge and K. Mayaram, A comparative analysis of CMOS low noise amplifiers for RF applications, Proc. of the 1998 IEEE Intl Symposium on Circuits and Systems, vol.4, pp. 349-352, 1998
4. J. Goo, K. Oh, C. Choi, Z. Yu, T. H. Lee and R. W. Dutton, Guidelines for the power constrained design of a CMOS tuned LNA, 2000 International Conference on Simulation of Semiconductor Processes and Devices, pp. 269-272, 2000
5. X. Li, H. Kim, M. Ismail and H. Olsson, A novel design approach for GHz CMOS low noise amplifiers, 1999 IEEE Radio and Wireless Conference, pp. 285-288, 1999
6. E. Sacchi, 1. Bietti, F. Gatta, F. Svelto and R. Castello, A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 94-97, 2000
7. S. Park and W. Kim, Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 Ion CMOS technology, IEEE Trans. on Consumer Electronics, vol. 47, No. 1, pp. 10-15, Feb. 2001
8. Y. Ding and R. Harjani, A +18 dBm 11P3 LNA in 0.35 im CMOS, 2001 IEEE Intl Solid-State Circuits Conference Digest of Technical Papers, pp. 162-163, 443, 2001
9. P. Leroux and M. Steyaert, High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection, Electronics Letters, vol. 37, No.7, pp. 467-469, March 2001
10. B. Razavi, A 5.2-Ghz CMOS receiver with 62-dB image rejection, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, pp. 810-815, May 2001
11. R. A. Rafla and M. N. El-Gamal, Design of a iSV CMOS integrated 3 GHz LNA, Proc the 1999 IEEE Intl Symposium on Circuits and Systems, vol. 2, pp. 440-443, 1999
12. Behzad Razavi, RF Microelectronics, Prentice Hall PTR, 1998
13. J. C. Huang, R. M. Weng, C. C. Chang, K. Hsu and K. Y. Lin, A 2V 2.4 GHz fully integrated CMOS LNA, Proc the 2001 IEEE Intl Symposium on Circuits and Systems, vol. 4, pp. 466-469, May 2001