SOI for hostile environment applications

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 1-4

  Colinge, J P ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONIC EQUIPMENT; HIGH TEMPERATURE EFFECTS; LEAKAGE CURRENTS; LOGIC GATES; MOSFET DEVICES; RADIATION EFFECTS; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE;

DOSE IRRADIATION; DOUBLE-GATE DEVICES; SINGLE-GATE DEVICES; VOLTAGE VARIATIONS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 10844269580     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. T.E. Rudenko et al., Microelectronic Engineering, Vol. 36, no. 1-4, p. 367, 1997
3. J.P. Colinge, Progress in SOI Structures and Devices Operating at Extreme Conditions, Kluwer Academic Publishers, pp. 167-188, 2002
4. G. Groeseneken et al., IEEE Electron Device Letters, Vol. 11, p. 329, 1990
5. F. Irom et al., Proceedings of the IEEE International SOI Conference, p. 203, 2002
6. P. Francis et al., IEEE Transactions on Nuclear Science, Vol. 42-6, pp.2127-2137, 1995
7. J.P. Colinge, Abstracts of NATO Advanced Research Workshop on Science and Technology of Semiconductor-on-Insulator Structures and Devices Operating in a Harsh Environment, Kiev, Ukraine, pp. 9-10, April 2004