Fault detection enhancement in cache memories using a high performance placement algorithm

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 101-106

  Zarandi, Hamid R ^a   Miremadi, Seyed Ghassem ^a   Sarbazi Azad, Hamid ^a,b  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^b Inst Studs Theor Phys and Maths   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

CONTENT ADDRESSABLE MEMORY (CAM); HIERARCHIAL SET-ASSOCIATIVE MAPPING (HSAM); TRANSIENT FAULT;

ALGORITHMS; COMPUTER HARDWARE; FAULT TOLERANT COMPUTER SYSTEMS; HIERARCHICAL SYSTEMS; MAPPING; PROBABILITY; RANDOM ACCESS STORAGE; RELIABILITY; VLSI CIRCUITS;

BUFFER STORAGE;

EID: 10444280013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319666     Document Type: Conference Paper

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