Data-flow timing models of dynamic multimedia applications for multiprocessor systems

Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

Volumn , Issue , 2004, Pages 206-209

  Pastrnak, Milan ^a,b   Poplavko, Peter ^b   De With, Peter N H ^a,b   Farin, Dirk S ^b  

^a LogicaCMG Nederland BV   (Netherlands)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION GRAPH; MULTIPROCESSOR ARCHITECTURES; SYNCHRONOUS DATA-FLOW (SDF) GRAPH; TIMING MODEL;

COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DATA ACQUISITION; DATA FLOW ANALYSIS; EMBEDDED SYSTEMS; GRAPH THEORY; MATHEMATICAL MODELS; MULTIMEDIA SYSTEMS; STORAGE ALLOCATION (COMPUTER); TIMING CIRCUITS;

MULTIPROCESSING SYSTEMS;

EID: 10444258171     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2004.1319879     Document Type: Conference Paper

References (4)

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3. R. Lauwereins, M. Engels, M. Ade, and J. A. Peperstraete, "Grape II: A system-level prototyping environment for DSP," in IEEE Transaction on Computer, February 1995, vol. 28 of 2, pp. 35-43.
4. M. Wan, H. Zhang, V. George, M. Benes, A. Abnous, V. Prabhu, and J. Rabaey, "Design methodology of a low-energy reconfigurable single-chip DSP systems," in Journal of VLSI Signal Processing, January 2001, vol. 28 of 1.