Design methodology of a low-energy reconfigurable single-chip DSP system

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 28, Issue 1-2, 2001, Pages 47-61

  Wan, M ^a   Zhang, H ^a   George, V ^a   Benes, M ^a   Abnous, A ^a   Prabhu, V ^a   Rabaey, J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Design methodology; Digital signal processor; Low power; Reconfigurable architecture

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS;

RECONFIGURABLE ARCHITECTURE;

DIGITAL SIGNAL PROCESSING;

EID: 0035341757     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008159121620     Document Type: Article

References (33)

1. A guide to using field programmable gate arrays for application-specific digital signal processing performance
2. Low-power equalizers for 51.84 Mb/s very high-speed digital subscriber loop [VDSL] modems
3. Ultra-low-power domain-specific multimedia processors
4. Evaluation of a low-power reconfigurable DSP architecture
5. Technologies for multimedia systems on a chip
6. Reconfigurable computing: The solution to low power programmable DSP
7. COSYN: Hardware-software consynthesis of embedded systems
8. Hardware/software co-design
9. GARP: A MIPS processor with a reconfigurable coprocessor
10. PRISC software acceleration techniques
11. Hardware/software partitioning of multi-function systems
12. An energy conscious methodology for early design exploration of heterogeneous DSPS
13. Early power exploration - A World Wide Web application
14. Instruction level power analysis and optimization of software
15. Black box capacitance models for architectural power analysis
16. Low energy FPGA design
17. Fast module mapping and placement for datapahs in FPGAs
18. Interconnect architecture exploration for low energy reconfigurable single-chip DSPs
19. Exploring the algorithmic design space using high level synthesis
20. Configuration prefetch for single context reconfigurable coprocessors
21. Performance-oriented placement and routing for field programmable gate arrays
22. Configuration code generation and optimizations for heterogeneous reconfigurable DSPs