Intermediate representations for design automation of multiprocessor DSP systems

Design Automation for Embedded Systems

Volumn 7, Issue 4, 2002, Pages 307-323

  Bambha, Neal ^a   Kianzad, Vida ^a   Khandelia, Mukul ^a   Bhattacharyya, Shuvra S ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Dataflow graphs; Digital signal processing; Embedded systems; Interprocessor communication; Self timed scheduling

Indexed keywords

COMPUTER PROGRAM LISTINGS; DATA COMMUNICATION SYSTEMS; DATA FLOW ANALYSIS; DATA TRANSFER; EMBEDDED SYSTEMS; RESOURCE ALLOCATION; SIGNAL PROCESSING; SYNCHRONIZATION;

DATAFLOW GRAPHS; DESIGN AUTOMATION; INTERPROCESSOR COMMUNICATION; MULTIPROCESSOR DIGITAL SIGNAL PROCESSING SYSTEM; SELF-TIMED SCHEDULING;

MULTIPROCESSING SYSTEMS;

EID: 0036847565     PISSN: 09295585     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1020307222052     Document Type: Article

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