Stacked thin dice packaging

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 361-366

  Pienimaa, S K ^a   Valtanen, J ^a   Heikkila R ^a   Ristolainen, E ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; ELECTRIC PROPERTIES; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; INTEGRATED CIRCUIT LAYOUT; PRINTED CIRCUIT BOARDS; RELIABILITY; SOLDERING ALLOYS; THICKNESS MEASUREMENT; THREE DIMENSIONAL;

FLIP CHIP ASSEMBLIES; MULTI-CHIP PACKAGES; SECOND GENERATION PACKAGES; SYSTEM-IN-PACKAGE SOLUTIONS;

ELECTRONICS PACKAGING;

EID: 0034835454     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2001.927749     Document Type: Article

References (14)

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