Effect of organic package core via pitch reduction on power distribution performance

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2004, Pages 1449-1453

  Audet, Jean ^a   O'Connor, Daniel P ^b   Grinberg, Mike ^b   Libous, James P ^b  

^a IBM CANADA LTD   (Canada)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP CARRIER; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS; ORGANIC PACKAGE CORE; PACKAGING SOLUTION;

CHARGE CARRIERS; CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; DIGITAL SIGNAL PROCESSING; ELECTRONICS PACKAGING; INPUT OUTPUT PROGRAMS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PHOTOLITHOGRAPHY; PRINTED CIRCUIT BOARDS; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO;

ELECTRIC POWER DISTRIBUTION;

EID: 10444222573     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. "International Technology Roadmap for Semiconductors," 2003 Edition, Semiconductor Industry Association
2. J.Audet, J.Wakil, D.West "Organic Chip Package Competitve Analysis" Internal IBM conference, August 2000
3. th Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 2002
4. P. A. Brennan, N. Raver, and A. E. Ruehli, "Three-Dimensional Inductance Computations with Partial Element Equivalent Circuits," IBM Journal of Research and Development, vol. 23, no. 6, pp. 661-668, Nov. 1979.
5. J. P. Libous and D. P. O'Connor, "Measurement, Modeling, and Simulation of Flip-Chip CMOS ASIC Simultaneous Switching Noise on a Multilayer Ceramic BGA", IEEE Trans, on Components, Packaging, and Manufacturing Technology, Part B, Vol.20, No. 3, pp.266-271, Aug. 1997.
6. th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 191-194, October, 1998
7. th Electronic Components and Technology Conf, New Orleans, LA, May. 2003, pp.450-455