Novel organic chip packaging technology and impacts on high speed interfaces

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn 2002-January, Issue , 2002, Pages 231-234

  Garben, Bernd ^a   Huber, Andreas ^a   Kaller, Dierk ^a   Mink, Erich ^a   Grivet Talocia, Stefanu ^b   Katopis, George A ^c  

^a IBM   (Germany)

^b POLITECNICO DI TORINO   (Italy)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION SYSTEMS; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; NONVOLATILE STORAGE; PACKAGING;

BUILD-UP LAYERS; CHIP PACKAGING TECHNOLOGIES; DEVELOPMENT ADVANCEMENTS; ELECTRICAL CHARACTERISTIC; HIGH-SPEED DATA TRANSMISSION; HIGH-SPEED INTERFACES; SINGLE-CHIP MODULES; TECHNOLOGY IMPROVEMENT;

CHIP SCALE PACKAGES;

EID: 10444282514     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2002.1057921     Document Type: Conference Paper

References (2)

1. Tummala, R. R., &licrosvstem Pack a,McG raw-Hill (New York, 2001), pp. 321. [packaging fundamentals. .]
2. Winkel T.; Kaller D. ; Huber A.: "Determination of Critical Line Length for On-Chip Interconnects for the Future Technologies as predicted in the SIA Roadmap", 4th IEEE Workshop on Signal Propagation on Interconnects, 2000