A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN Systems

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages

  Zargari, Masoud ^a   Su, David K ^a   Yue, C Patrick ^a   Rabii, Shahriar ^b   Weber, David ^a   Kaczynski, Brian J ^a   Mehta, Srenik S ^a   Singh, Kalwant ^a   Mendis, Sunetra ^a   Wooley, Bruce A ^c  

^a Atheros Communications   (United States)

^b Aeluros Inc   (United States)

^c STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CLOSED LOOP CONTROL SYSTEMS; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); DIGITAL TO ANALOG CONVERSION; ELECTRIC FILTERS; FREQUENCY SYNTHESIZERS; LOCAL AREA NETWORKS; POWER AMPLIFIERS; POWER CONTROL; QUADRATURE AMPLITUDE MODULATION; QUADRATURE PHASE SHIFT KEYING; RADIO SYSTEMS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS; WIRELESS TELECOMMUNICATION SYSTEMS;

WIRELESS LOCAL AREA NETWORKS (WLAN);

TRANSCEIVERS;

EID: 0036116458     PISSN: 01936530     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.804353     Document Type: Article

References (2)

1. Wireless LAN MAC and PHY specifications - High-speed physical layer in the 5 GHz band
2. An Integrated 802.11a baseband and MAC processor