A CMOS dual-band tri-mode chipset for IEEE 802.11a/b/g Wireless LAN

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2003, Pages 427-430

  Mehta, S ^a   Zargari, M ^a   Jen, S ^a   Kaczynski, B ^a   Lee, M ^a   Mack, M ^a   Mendis, S ^a   Onodera, K ^a   Samavati, H ^a   Si, W ^a   Singh, K ^a   Terrovitis, M ^a   Weber, D ^a   Su, D ^a  

^a Atheros Communications   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; LOCAL AREA NETWORKS; SENSITIVITY ANALYSIS; TRANSCEIVERS;

TRI-MODE CHIPSET;

MICROPROCESSOR CHIPS;

EID: 0043091884     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Thomson, et. al., "An Integrated 802.11a Baseband and MAC Processor," 2002 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 126-127, 2002.
2. D. Su, et. al., "A 5GHz CMOS Transceiver for IEEE 802.11a Wireless LAN," 2002 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 92-93, 2002.
3. "Range and Throughput Comparisons of WLAN Products," Atheros Communications, 〈http://www.atheros.com/pt/atheros_range2.pd〉, 2003.