Performance and reliability of low-temperature polysilicon TFT with a novel stack gate dielectric and stack optimization using PECVD nitrous oxide plasma

IEEE Transactions on Electron Devices

Volumn 51, Issue 1, 2004, Pages 63-67

  Chang, Kow Ming ^a   Yang, Wen Chih ^a   Tsai, Chiu Pao ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Dielectric films; Gate oxide; Nitrous oxide plasma; Polycrystalline silicon thin film transistor (polysilicon TFT); Reliability

Indexed keywords

AMORPHOUS SILICON; CARRIER CONCENTRATION; CHEMICAL BONDS; DIELECTRIC FILMS; ELECTRIC BREAKDOWN; INTERFACES (MATERIALS); NITROGEN OXIDES; OPTIMIZATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; PLASMAS; POLYSILICON; RELIABILITY;

BULK TRAP DENSITY; NITROUS OXIDE PLASMA; POLYSILICON THIN FILM TRANSISTOR; STACK GATE DIELECTRIC; TETRAORTHOSILICATE OXYNITRIDE;

THIN FILM TRANSISTORS;

EID: 0742304013     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.820791     Document Type: Article

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