High-performance FPGA implementation of DES using a novel method for implementing the key schedule

IEE Proceedings: Circuits, Devices and Systems

Volumn 150, Issue 5, 2003, Pages 373-378

  McLoone, M ^a   McCanny, J V ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; CRYPTOGRAPHY; DATA COMMUNICATION SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; RANDOM ACCESS STORAGE; SECURITY OF DATA; STANDARDS;

DATA ENCRYPTION STANDARD; KEY SCHEDULING CORE; PIPELINED PRIVATE-KEY ENCRYPTION ALGORITHM;

ALGORITHMS;

EID: 0346947091     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20030574     Document Type: Article

References (15)

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