A case study of partially evaluated hardware circuits: Key-specific DES

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1304, Issue , 1997, Pages 151-160

  Leonard, Jason ^a   Mangione Smith, William H ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84947936197     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_220     Document Type: Conference Paper

References (10)

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2. J. P. Gray and T. A. Kean, “Configurable Hardware: A New Paradigm for Computation,” presented at Decennial Cal Tech Conference on VLSI, Pasadena, CA, 1989.
3. M. Blaze, W. Diffie, R. L. Rivest, B. Schneier, T. Shimomura, E. Thompson, and M. Wiener, “Minimal Key Lengths for Symmetric Ciphers to Provide Adequate Commercial Security: A Report by an ad hoc Group of Cryptographers and Computer Scientists,” http://www.bsa.org/policy/encryption/cryptographers, 1996.
4. I. Goldberg and D. Wagner, “Architectural Considerations for Cryptoanalytic Hardware,” http://www.cs.berkeley.edu/~iang/isaac/hardware, 1996.
5. S. Son, “Feasibility Study: DES Cryptanalysis Using Reconfigurable Hardware,” ftp://ftp.et.byu.edu/papers/ desfpga.ps, 1996.
6. W. Diffie and M. E. Heilman, “Exhaustive Cryptanalysis of the NBS Data Encryption Standard,” in IEEE Computer, vol.10, 1977, pp. 74-84.
7. M. J. Wiener, “Efficient DES Key Search,” presented at CRYPTO ’93, Santa Barbara, CA, 1993.
8. J. Villasenor, B. Schoner, K. Chia, C. Zapata, H. J. Kim, C. Jones, S. Lansing, and W. H. Mangione-Smith, “Configurable Computing Solutions for Automatic Target Recognition,” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K. L. Pocek, Eds. Napa, CA, 1996, pp. 7079.
9. S. Singh, J. Hogg, and D. McAuley, “Expressing Dynamic Reconfiguration by Partial Evaluation,” presented at Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, 1996.
10. Q. Wang and D. M. Lewis, “Automated Field-Programmable Compute Accelerator Design Using Partial Evaluation,” presented at Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, 1997.