Gigabit Ethernet Switches Using a Shared Buffer Architecture

IEEE Communications Magazine

Volumn 41, Issue 12, 2003, Pages 76-84

  Lau, Michael V ^a,b   Shieh, Sam ^a,c   Wang, Pei Feng ^a   Smith, Brandon ^a   Lee, Dennis ^a   Chao, Jason ^a   Shung, Bernard ^a,d,e,f   Shih, Cheng Chung ^g  

^a BROADCOM CORPORATION   (United States)

^b Cirrus Logic   (United States)

^c NVIDIA   (United States)

^d IBM ALMADEN RESEARCH CENTER   (United States)

^e NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^f QUALCOMM INC   (United States)

^g Broadcom Asia Design Centers

Author keywords

[No Author keywords available]

Indexed keywords

ETHERNET SWITCHES; NETWORK INTERFACE CARD (NIC);

CMOS INTEGRATED CIRCUITS; MULTIMEDIA SYSTEMS; ROUTERS; SIGNAL PROCESSING; SWITCHES; VLSI CIRCUITS; WIDE AREA NETWORKS;

TELECOMMUNICATION NETWORKS;

EID: 0346752335     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCOM.2003.1252802     Document Type: Article

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