Design and component test of RSFQ packet decoders for shift register memories

Physica C: Superconductivity and its Applications

Volumn 378-381, Issue PART 2, 2002, Pages 1475-1480

  Fujiwara, K ^a   Hoshina, H ^a   Koshiyama, J ^a   Yoshikawa, N ^a  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

Data drive self timing; Memory; RSFQ circuits; SFQ; Shift register; Superconducting device

Indexed keywords

DIGITAL STORAGE; FREQUENCIES; MICROPROCESSOR CHIPS; PACKET SWITCHING; SHIFT REGISTERS; SUPERCONDUCTING DEVICES; SYNCHRONIZATION; TIMING CIRCUITS;

PACKET DECODERS;

DECODING;

EID: 0012306549     PISSN: 09214534     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0921-4534(02)01760-4     Document Type: Article

References (4)

1. Likharev K.K., Semenov V.K. IEEE Trans. Appl. Supercond. 1:1992;1.
2. Fujimaki A., Takai Y., Yoshikawa N. IEICE Trans. Electron. E85-C:2002;612.
3. Deng Z.J., Yoshikawa N., Whiteley S.R., Van Duzer T. IEEE Trans. Appl. Supercond. 9:1999;7.
4. Yoshikawa N., Tago H., Yoneyama K. IEEE Trans. Appl. Supercond. 9:1999;3161.