Push-pull production planning of the re-entrant process

International Journal of Advanced Manufacturing Technology

Volumn 22, Issue 11-12, 2003, Pages 922-931

  Lee, Young Hoon ^a   Lee, Byungjin ^a  

^a Yonsei University   (South Korea)

Author keywords

Optimisation; Push and pull control; Semiconductor; TFT LCD

Indexed keywords

LINEAR PROGRAMMING; LIQUID CRYSTAL DISPLAYS; PRODUCTION CONTROL; THIN FILM TRANSISTORS;

CONTROL POLICY; PRODUCTION PLANNING;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0346276733     PISSN: 02683768     EISSN: None     Source Type: Journal    
DOI: 10.1007/s00170-003-1653-7     Document Type: Article

References (15)

1. Spearman ML, Zazanis MA (1992) Push and pull production systems: issues and comparisons. Ops Res 40(3):521-532
2. Wein LM (1988) Scheduling semiconductor wafer fabrication. IEEE Trans Semicond Manufact 1:115-129
3. Glassey CR, Resende MGC (1988) Closed-loop job release control for VSLI circuit manufacturing. IEEE Trans Semicond Manufact 1:36-46
4. Glassey CR, Resende MGC (1988) A scheduling rule for job release in semiconductor fabrication. Ops Res Lett 7:213-217
5. Spearman ML, Woodruff DL and Hopp WJ (1990) CONWIP: a pull alternative to kanban. Int J Prod Res 28:879-894
6. Pierce NG, Yurtsever T (2000) Value-based dispatching for semiconductor wafer fabrication. In: Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing, Tempe, AZ, 10-12 May 2000
7. Morrison J, Janakiram M and Kumar PR (1999) A comparative study of scheduling policies at Motorola fabs. In: Proceedings of the International Conference on Semiconductor Manufacturing Operational Modeling and Simulation, San Francisco, CA, 18-20 January 1999
8. Kim H, Kim Y and Kim J (2000) Batching and scheduling at batch processing workstation in a semiconductor fabrication facility producing multiple product types with distinct due dates. In: Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing, Tempe, AZ, 10-12 May 2000
9. Ehteshami B, Petrakian RG and Shabe PM (1992) Trade-offs in cycle time management: hot lots. IEEE Trans Semicond Manufact 5:101-106
10. Chaoyang L, Weidong L and Souza RD (1999) The dynamics of semiconductor line and cycle time. In: Proceedings of the International Conference on Semiconductor Manufacturing Operational Modeling and Simulation, San Francisco, CA, 18-20 January 1999
11. Robinson J and Chance F (2000) Wafer fabrication cycle time management using MES data. In: Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing, Tempe, AZ, 10-12 May 2000
12. Rose O (1999) Estimation of the cycle time distribution of a wafer fab by a simple simulation model. In: Proceedings of the International Conference on Semiconductor Manufacturing Operational Modeling and Simulation, San Francisco, CA, 18-20 January 1999
13. Kim S, Yea S and Kim B (2000) Stepper scheduling in semiconductor wafer fabrication process. In: Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing, Tempe, AZ, 10-12 May 2000
14. Kim S, Yea S-H and Kim B (2002) Shift scheduling for steppers in the semiconductor wafer fabrication process. IIE Trans 34:167-177
15. Lee YH, Park J and Kim S (2002) Experimental study on input and bottleneck scheduling for the semiconductor fabrication line. IIE Trans 34:179-190