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Volumn 34, Issue 2, 2002, Pages 179-190

Experimental study on input and bottleneck scheduling for a semiconductor fabrication line

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EID: 0036468738     PISSN: 0740817X     EISSN: 15458830     Source Type: Journal    
DOI: 10.1080/07408170208928860     Document Type: Article
Times cited : (60)

References (26)
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    • Glassey, C.R.1    Resende, M.G.C.2
  • 11
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    • Kraft, C.1
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    • A heuristic to minimize the total weighted tardiness with sequence-dependent setups
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  • 14
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    • Lee, Y.H., and Pinedo, M., (1997) Scheduling jobs on parallel machines with sequence-dependent setup times. European Journal of Operational Research, 100, 464–474.
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    • A review of production planning and scheduling models in the semiconductor industry
    • part I: system characteristics, performance evaluation, and production planning
    • Uzsoy, R., Lee, C.Y., and Martin-Vega, L.A., (1992) A review of production planning and scheduling models in the semiconductor industry, part I:system characteristics, performance evaluation, and production planning. IIE Transactions, 24, 47–60.
    • (1992) IIE Transactions , vol.24 , pp. 47-60
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    • part II: shop-floor control
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    • (1994) IIE Transactions , vol.26 , pp. 44-55
    • Uzsoy, R.1    Lee, C.Y.2    Martin-Vega, L.A.3
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    • Vepsalainen, A., and Morton, T.E., (1987) Priority rules for job shops with weighted tardiness costs. Management Science, 33, 1035–1047.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.