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Volumn 2299, Issue , 2002, Pages 179-191

Cached two-level adaptive branch predictors with multiple stages

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; NETWORK ARCHITECTURE; UBIQUITOUS COMPUTING;

EID: 0345340029     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45997-9_14     Document Type: Conference Paper
Times cited : (2)

References (16)
  • 3
    • 84947244457 scopus 로고    scopus 로고
    • IA-64 Application Developer.s Guide, Intel, (2000).
    • (2000) Intel
  • 4
    • 0032639289 scopus 로고    scopus 로고
    • The Alpha 21264 Microprocessor
    • Kessler, R. E.: The Alpha 21264 Microprocessor, IEEE Micro, (1999), 24-36.
    • (1999) IEEE Micro , pp. 24-36
    • Kessler, R.E.1
  • 8
    • 0027307813 scopus 로고
    • A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History
    • Yeh, T. and Patt, Y. N.: A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History, ISCA - 20, (1993), 257-266.
    • (1993) ISCA - , vol.20 , pp. 257-266
    • Yeh, T.1    Patt, Y.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.