-
1
-
-
85034094146
-
-
Albuquerque, New Mexico
-
Yeh, T. and Patt, Y. N.: Two-Level Adaptive Training Branch Prediction, Micro-24, Albuquerque, New Mexico, (1991), 51-61.
-
(1991)
Two-Level Adaptive Training Branch Prediction, Micro-24
, pp. 51-61
-
-
Yeh, T.1
Patt, Y.N.2
-
2
-
-
0026918390
-
-
ASPLOS-V, Boston
-
Pan, S.; So, K. and Rahmeh, J. T.: Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation, ASPLOS-V, Boston, (1992), 76-84.
-
(1992)
Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation
, pp. 76-84
-
-
Pan, S.1
So, K.2
Rahmeh, J.T.3
-
3
-
-
84947244457
-
-
IA-64 Application Developer.s Guide, Intel, (2000).
-
(2000)
Intel
-
-
-
4
-
-
0032639289
-
The Alpha 21264 Microprocessor
-
Kessler, R. E.: The Alpha 21264 Microprocessor, IEEE Micro, (1999), 24-36.
-
(1999)
IEEE Micro
, pp. 24-36
-
-
Kessler, R.E.1
-
6
-
-
0344046197
-
A Cost Effective Cached Correlated Two-level Adaptive Branch Predictor
-
Innsbruck
-
Steven, G. B.; Egan, C.; Quick, P. and Vintan, L.: A Cost Effective Cached Correlated Two-level Adaptive Branch Predictor, 18th IASTED International Conference on Applied Informatics (AI 2000), Innsbruck, (2000).
-
(2000)
18Th IASTED International Conference on Applied Informatics (AI 2000
-
-
Steven, G.B.1
Egan, C.2
Quick, P.3
Vintan, L.4
-
7
-
-
0026867221
-
-
ISCA-19, Gold Coast, Australia
-
Yeh, T. and Patt, P.: Alternative Implementations of Two-Level Adaptive Branch Prediction, ISCA-19, Gold Coast, Australia, (1992), 124-134.
-
(1992)
Alternative Implementations of Two-Level Adaptive Branch Prediction
, pp. 124-134
-
-
Yeh, T.1
Patt, P.2
-
8
-
-
0027307813
-
A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History
-
Yeh, T. and Patt, Y. N.: A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History, ISCA - 20, (1993), 257-266.
-
(1993)
ISCA -
, vol.20
, pp. 257-266
-
-
Yeh, T.1
Patt, Y.N.2
-
10
-
-
0028767981
-
-
Micro-27, San Jose, California
-
Chang, P., Hao, E., Yeh, T. and Patt, Y. N.: Branch Classification: A New Mechanism for Improving Branch Predictor Performance, Micro-27, San Jose, California, (1994), 22-31.
-
(1994)
Branch Classification: A New Mechanism for Improving Branch Predictor Performance
, pp. 22-31
-
-
Chang, P.1
Hao, E.2
Yeh, T.3
Patt, Y.N.4
-
11
-
-
0031338573
-
-
Micro-30, Research Triangle Park, North Carolina
-
Lee, C. C., Chen, I. K. and Mudge, T. N.: The Bi-Mode Branch Predictor, Micro-30, Research Triangle Park, North Carolina, (1997), 4-13.
-
(1997)
The Bi-Mode Branch Predictor
, pp. 4-13
-
-
Lee, C.C.1
Chen, I.K.2
Mudge, T.N.3
-
12
-
-
0030672489
-
-
Denver, Colorado
-
Sprangle, E., Chappell, R. S., Alsup, M. and Patt, Y. N.: The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference, ISCA.24, Denver, Colorado, (1997), 284-291.
-
(1997)
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference, ISCA.24
, pp. 284-291
-
-
Sprangle, E.1
Chappell, R.S.2
Alsup, M.3
Patt, Y.N.4
-
13
-
-
2842579283
-
-
ASPLOS VII
-
Chen, I. K., Coffey, J. T. and Mudge, T. N.: Analysis of Branch Prediction via Data Compression, ASPLOS VII, (1996), 128-137.
-
(1996)
Analysis of Branch Prediction via Data Compression
, pp. 128-137
-
-
Chen, I.K.1
Coffey, J.T.2
Mudge, T.N.3
-
14
-
-
84969584440
-
-
DSD 2001, Poland
-
Steven, G., Anguera, R., Egan, C., Steven, F. and Vintan, L.: Dynamic Branch Prediction Using Neural Networks, DSD 2001, Poland, (2001), 178-185.
-
(2001)
Dynamic Branch Prediction Using Neural Networks
, pp. 178-185
-
-
Steven, G.1
Anguera, R.2
Egan, C.3
Steven, F.4
Vintan, L.5
-
15
-
-
0029511543
-
-
Micro-29, Ann Arbor, Michigan
-
Chang, L, Hao E. and Patt, Y. N.: Alternative Implementations of Hybrid Branch Predictors, Micro-29, Ann Arbor, Michigan, (1995), 252-257.
-
(1995)
Alternative Implementations of Hybrid Branch Predictors
, pp. 252-257
-
-
Chang, L.1
Hao, E.2
Patt, Y.N.3
-
16
-
-
0042045541
-
A Superscalar Architecture to Exploit Instruction Level Parallelism
-
Steven, G. B., Christianson, D. B., Collins, R., Potter, R. D. and Steven, F. L.: A Superscalar Architecture to Exploit Instruction Level Parallelism, Microprocessors and Microsystems, 20 (7), (1997), 391-400.
-
(1997)
Microprocessors and Microsystems
, vol.20
, Issue.7
, pp. 391-400
-
-
Steven, G.B.1
Christianson, D.B.2
Collins, R.3
Potter, R.D.4
Steven, F.L.5
|