A superscalar architecture to exploit instruction level parallelism

Microprocessors and Microsystems

Volumn 20, Issue 7, 1997, Pages 391-400

  Steven, Gordon ^a   Christianson, Bruce ^a   Collins, Roger ^a   Potter, Richard ^a   Steven, Fleur ^a  

^a UNIVERSITY OF HERTFORDSHIRE   (United Kingdom)

Author keywords

Instruction scheduling; Multiple instruction issue; Superscalar

Indexed keywords

PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; REDUCED INSTRUCTION SET COMPUTING;

HATFIELD SUPERSCALAR ARCHITECTURE (HSA); MULTIPLE INSTRUCTION ISSUE (MII);

MICROPROCESSOR CHIPS;

EID: 0042045541     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0141-9331(96)01101-5     Document Type: Article

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