Toward performance-driven reduction of the cost of RET-based lithography control

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5043, Issue , 2003, Pages 123-133

  Gupta, Puneet ^a   Kahng, Andrew B ^a   Sylvester, Dennis ^b   Yang, Jie ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of Michigan   (United States)

Author keywords

Correction; OPC; RET; Variability

Indexed keywords

BUDGET CONTROL; ELECTRONICS INDUSTRY; INDUSTRIAL ECONOMICS; MASKS; OPTICAL RESOLVING POWER; PHOTOLITHOGRAPHY; PROBABILITY DENSITY FUNCTION; STATISTICAL METHODS;

COST OF OWNERSHIP; CRITICAL DIMENSION; DIMENSIONAL VARIATION CONTROL; OPTICAL PROXIMITY CORRECTION; PHASE SHIFT MASK; RESOLUTION ENHANCEMENT TECHNIQUES;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0344440763     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.485277     Document Type: Conference Paper

References (19)

1. International Technology Roadmap for Semiconductors, December 2001 http://public.itrs.net/
2. Y. Cao, P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, "Design Sensitivities to Variability: Extrapolations and Assessments in Nanometer VLSI", IEEE International ASIC/SOC Conference, 2002, pp. 411-415.
3. "The Outlook for Semiconductor Processes and Manufacturing Technologies in the 0.1-μm Age", http://www.cyberfab.net/events/013mmts /links013.html.
4. M.L. Rieger, J.P. Mayhew, and S. Panchapakesan, "Layout Design Methodologies for Sub-Wavelength Manufacturing", Proceedings of Design Automation Conference, 2001, pp. 85-92.
5. SEMATECH: Mask Supply Workshop, 2001.
6. Chiang Yang, "Challenges of Mask Cost and Cycle Time", SEMATECH: Mask Supply Workshop, Intel, 2001.
7. W. Carpenter, "International SEMATECH: A Focus on the Photomask Industry", http://www.klatencor.com/company_info/magazine/autumn00/Inter_ SEMATECH_photomaskindustry_AutumnMag00-3.pdf.
8. B. Bruggeman, et al, "Microlithography Cost Analysis", Interface Symposium, 1999.
9. S. Murphy, Dupont Photomask, SEMATECH: Mask Supply Workshop, 2001.
10. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Statistical Timing Analysis using Bounds and Selective Enumeration", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp. 29-36.
11. Robert R. Kinnison, Applied Extreme Value Statistics, Battelle Press, 1985.
12. W. Chuang, S.S. Sapatnekar and I.N. Hajji, "Delay and Area Optimization for Discrete Gate Sizes under Double-Sided Timing Constraints", Proc. IEEE Custom Integrated Circuits Conference, 1993, pp. 9.4.1-9.4.4.
13. A.E. Dunlop, J.P. Fishburn, D.D. Hill and D.D. Shugard, "Experiments using Automatic Physical Design Techniques for Optimizing Circuit Performance", Proc. IEEE International Symposium on Circuits and Systems, (2), 1990, pp. 847-851.
14. R. Nair, C.L. Berman, P.S. Hauge and E.J. Yoffa, "Generation of Performance Constraints for Layout", IEEE Transactions on Computer Aided Design, 8(8), 1989, pp. 860-874.
15. M. Sarrafzadeh, D.A. Knol and G.E. Tellez, "A Delay Budgeting Algorithm Ensuring Maximum Flexibility in Placement", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 16(11), 1997, pp. 1332-1341.
16. D. Pramanik, Numerical Technologies Inc., personal communication, November 2002.
17. Synopsys Design Compiler, http://www.synopsys.com/products/logic/logic.html
18. P. Buck, ISMT Mask-EDA Workshop, Dupont Photomasks, 2001.
19. K. Wampler, ASML MaskTools, personal communication, March 2003.