Dynamic operand interchange for low power

Electronics Letters

Volumn 33, Issue 25, 1997, Pages 2118-2120

  Ahn, Taekyoon ^a   Choi, Kiyoung ^a  

^a NONE

Author keywords

Computer architecture; VLSI

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DECISION THEORY; LOGIC CIRCUITS; MULTIPLYING CIRCUITS; SHIFT REGISTERS;

OPERAND INTERCHANGE METHOD;

VLSI CIRCUITS;

EID: 0031553153     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19971440     Document Type: Article

References (6)

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2. TIWARI, V., MALIK, S., and ASHAR, P.: 'Guarded evaluation: pushing power management to logic synthesis/design'. Proc. Int. Symp. on Low power Design, 1995, pp. 221-226
3. MUSOLL, E., and CORTADELLA, J.: 'Scheduling and resource binding for low power'. Proc. Int. Symp. on System Synthesis, 1995, pp. 104-109
4. LEE, T.-C., TIWARI, V., MALIK, S., and FUJITA, M.: 'Power analysis and minimisation techniques for embedded DSP software', IEEE Trans. VLSI Syst., 1997, 5, (1), pp. 123-135
5. RAGHUNATHAN, A., DEY, S., and JHA, N.: 'Glitch analysis and reduction in register transfer level power optimisation'. Proc. Design Automation Conf., 1996, pp. 331-336
6. RABAEY, J., CHU, C., HOANG, P., and POTKONJAK, M.: 'Fast prototyping of datapath-intensive architecture', IEEE Trans. Comput. Aided Des., 1991, 10, (7), pp. 847-860