Boosting the performance of shared memory multiprocessors

Computer

Volumn 30, Issue 7, 1997, Pages 63-70

  Stenström, Per ^a,b,e   Brorsson, Mats ^b,e   Dahlgren, Fredrik ^a,e   Grahn, Håkan ^b,c,e   Dubois, Michel ^d,e,f,g,h,i  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

^b LUND UNIVERSITY   (Sweden)

^c University of Karlskrona   (Sweden)

^d UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^e IEEE

^f IEEE Computer Society ^*  (United States)

^g PURDUE UNIVERSITY   (United States)

^h UNIVERSITY OF MINNESOTA   (United States)

ⁱ UNIVERSITY OF MONS   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

SHARED MEMORY MULTIPROCESSORS;

MULTIPROCESSING SYSTEMS; RANDOM ACCESS STORAGE;

BUFFER STORAGE;

EID: 0031186448     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.596630     Document Type: Review

References (13)

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3. P. Stenström, M. Brorsson, and L. Sandberg, "An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1993, pp. 109-118.
4. H. Grahn, P. Stenström, and M. Dubois, "Implementation and Evaluation of Update-Based Cache Protocols Under Relaxed Memory Consistency Models," Future Generation Computer Systems, June 1995, pp. 247-271.
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7. M. Dubois and C. Scheurich, "Memory-Access Dependencies in Shared-Memory Multiprocessors," IEEE Trans. Software Eng., June 1990, pp. 660-673.
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9. T.F. Chen and J.L. Baer, "A Performance Study of Software and Hardware Data Prefetching Schemes," Proc. Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1994, pp. 223-233.
10. T. Mowry, M. Lam, and A. Gupta, "Design and Evaluation of a Compiler Algorithm for Prefetching," Proc. Conf. Architectural Support for Programming Languages and Operating Systems, ACM, New York, 1992, pp. 62-75.
11. A. Cox and R. Fowler, "Adaptive Cache Coherency for Detecting Migratory Shared Data," Proc. Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1993, pp. 98-108.
12. C. Anderson and A. Karlin, "Two Adaptive Cache Coherency Protocols," Proc. Symp. High-Performance Computer Architecture, IEEE CS Press, Los Alamitos, 1996, pp. 303-313.
13. E. Hagersten, A. Landin, and S. Haridi, "DDM: A Cache-Only Memory Architecture," Computer, Sept. 1992, pp. 44-54.