Logic restructuring for MUX-based FPGAs

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 1999, Pages 161-168

  Espejo, J A ^a   Entrena, L ^a   Millan, E S ^a   Olias, E ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE ESTIMATION; CIRCUIT DESCRIPTION; DELAY ESTIMATION; DELAY OPTIMIZATION; INCREMENTAL TRANSFORMATION; LOGIC OPTIMIZATION; LOGIC RESTRUCTURING; MUX-BASED;

AUTOMATIC TEST PATTERN GENERATION; INFORMATION SCIENCE; OPTIMIZATION; TOOLS;

NETWORK ARCHITECTURE;

EID: 0342557272     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1999.794462     Document Type: Conference Paper

References (14)

1. R. Murgai, R. K. Brayton, A. Sangiovanni-Vincentelli. "Logic Synthesis for Field-Programmable Gate Arrays". Ed. Kluwer Academic Publishers, 1995
2. K. J. Singh, A. R. Wang, R. K. Brayton, A. Sangiovanni-Vincentelli. "Timing Optimization of Combinational Logic". Proc. ICCAD-88, p.282-285, Nov. 1988.
3. B. Rohfleisch, B. Wurth, K. Antreich. "Logic Clause Analysis for Delay Optimization". Proc. 32nd DAC, p. 668-672. June 1995.
4. K. C. Chen y S. Muroga. "Timing Optimization for Multi-Level Combinational Networks". Proc. 27th DAC, p. 339-344. June 1990.
5. L. A. Entrena, K.-T. Cheng. "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal". IEEE Transactions on CAD, vol.14, n. 7, p. 909-916. July, 1995.
6. L. A. Entrena, J. A. Espejo, E. Olías, J. Uceda. "Timing optimization by an improved redundancy addition and removal technique". Proc. EURODAC'96, p. 342-347. Sept. 1996
7. Y. M. Yiang, A. Krstic, K.-T. Cheng, M. Marek-Sadowska. "Post-layout logic restructuring for Performance Optimization". Proc. 34th DAC. June 1997.
8. S.-C. Chang, K.-T. Cheng, N.-S. Woo, M. Marek-Sadowska. "Post-layout logic restructuring using alternative wires". IEEE Transactions on CAD, vol.16, n. 6, p. 587-596. June, 1997.
9. W. Kunz, P. Menon. "Multi-Level Logic Optimization by Implication Analysis". Proc. ICCAD-94, p. 6-13. November 1994
10. W. Kunz, D. Stoffel. "Reasoning in Boolean Networks". Ed. Kluwer Academic Publishers, 1997
11. B. Rohfleisch, F. Brglez. "Introduction of permissible bridges with application to logic optimization after technology mapping". Proc. European Design &Test Conference (ED&TC), p. 87-93. February 1994.
12. "SIS: A System for Sequential Circuit Synthesis" Report M92/41, University of California, Berkeley, May. 1992.
13. "FPGA Data Book and Design Guide". Actel Corporation 1996.
14. "Macro Library Summary" FPGA Release 2.2. Texas Instruments 1993.