A low-jitter mixed DLL for high-speed DRAMs

European Solid-State Circuits Conference

Volumn , Issue , 1999, Pages 134-137

  Kim, Jae Joon ^a   Kim, Beomsup ^a   Lee, Sangbo ^b   Cho, Soo In ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TUNING; CMOS PROCESSS; DELAY-LOCKED LOOPS; DIGITAL DELAY LINES; FAST-LOCKING; LOW POWER; LOW-JITTER PERFORMANCE; RMS JITTER;

CMOS INTEGRATED CIRCUITS; LOCKS (FASTENERS);

JITTER;

EID: 0342377541     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. J. G. Maneatis, "Low-Jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques", ISSCC Digest of Technical Papers, pp. 130-131, Feb., 1998.
2. C. Kim, et al., "A 640MB/s Bi-Directional Data Strobed, Double-Data-Rate SDRAM with a 40mW DLL Circuit for a 256MB Memory System", ISSCC Digest of Technical Papers, pp. 158-159, Feb., 1998.
3. T. Saeki, et al., "A 2.5-ns Clock Access, 250MHz, 256Mb DRAM with Synchronous Mirror Delay", IEEE J. Solid-State Circuits, vol. 31, pp. 1656-1668, Nov. 1998.
4. T. Yoshimura, et al., "A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories", Symposium on VLSI Circuits Digest of Technical Papers, pp. 66-67, 1998.
5. B. W. Garlepp, et al., "A Portable Digital DLL Architecture for CMOS Interface Circuits", Symposium on VLSI Circuits Digest of Technical Papers, pp. 214-215, 1998.
6. Y. Okajima, et al., "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface", IEICE Technical Report, pp.798-807, June, 1996.
7. G. Geannopoulos, X. Dai, "An Adaptive Digital Deskewing Circuit for Clock Distribution Networks", ISSCC Digest of Technical Papers, pp. 400-401, Feb., 1998.