Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets

IEEE Transactions on Instrumentation and Measurement

Volumn 52, Issue 5, 2003, Pages 1363-1380

  Das, Sunil R ^a   Sudarma, Made ^a   Assaf, Mansour H ^a   Petriu, Emil M ^a   Jone, Wen Ben ^b   Chakrabarty, Krishnendu ^c   Şhinoǧlu, Mehmet ^d  

^a UNIVERSITY OF OTTAWA   (Canada)

^b 705 Engineering Research Center   (United States)

^c Duke University   (United States)

^d TROY UNIVERSITY   (United States)

Author keywords

Built in self test (BIST); Circuit under test (CUT); Multiple output parity bit signature generation; Nonexhaustive or compact test sets; Parity testing; Space time compaction; Stuck line faults; Time compaction

Indexed keywords

BUILT-IN SELF TEST; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

CIRCUIT UNDER TEST; MULTIPLE OUTPUT PARITY BIT SIGNATURE GENERATION; PARITY TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0242636492     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2003.818547     Document Type: Article

References (37)

1. P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Technique. New York: Wiley, 1987.
2. S. Mourad and Y. Zorian, Principles of Testing Electronic Systems. New York: Wiley, 2000.
3. T. W. Williams and K. P. Parker, "Testing logic networks and design for testability," Computer, vol. 21, pp. 9-21, Oct. 1979.
4. E. J. McCluskey, "Built-in self-test techniques," IEEE Design Test Comput., vol. 2, pp. 21-28, Apr. 1985.
5. R. G. Daniels and W. B. Bruce, "Built-in self-test trends in Motorola microprocessors," IEEE Design Test Comput., vol. 2, pp. 64-71, Apr. 1985.
6. J. P. Hayes, "Check sum methods for test data compression," J. Design Automat. Fault-Tolerant Comput., vol. 1, pp. 3-7, Jan. 1976.
7. ____, "Transition count testing of combinatorial logic circuits," IEEE Trans. Comput., vol. C-25, pp. 613-620, June 1976.
8. R. A. Frohwerk, "Signature analysis - A new digital field service method," Hewlett-Packard J., vol. 28, pp. 2-8, May 1977.
9. J. Savir, "Syndrome-testable design of combinational circuits," IEEE Trans. Comput., vol. C-29, pp. 442-451, June 1980.
10. A. K. Susskind, "Testing by verifying Walsh coefficients," IEEE Trans. Comput., vol. C-32, pp. 198-201, Feb. 1983.
11. N. R. Saxena and J. P. Robinson, "A unified view of test response compression methods," IEEE Trans. Comput., vol. C-36, pp. 94-99, Jan. 1987.
12. T. W. Williams, W. Daehn, M. Gruentzner, and C. W. Starke, "Aliasing errors in signature analysis registers," IEEE Design Test Comput., vol. 4, pp. 39-45, Apr. 1987.
13. N. R. Saxena and J. P. Robinson, "Syndrome and transition count are uncorrelated," IEEE Trans. Inform. Theory, vol. 34, pp. 64-69, Jan. 1988.
14. S. B. Akers, "A parity bit signature for exhaustive testing," IEEE Trans. Comput. Aided Design, vol. 7, pp. 333-338, Mar. 1988.
15. W. B. Jone and S. R. Das, "Multiple-output parity bit signature for exhaustive testing," J. Electron. Testing: Theory Applicat., vol. 1, pp. 175-178, Mar. 1990.
16. N. S. Khabra and S. R. Das, "Multiform partial symmetry and parity functions," IEEE Trans. Comput., vol. C-22, p. 804, Aug. 1973.
17. D. K. Pradhan and S. K. Gupta, "A new framework for designing and analyzing BIST techniques and zero aliasing compression," IEEE Trans. Comput., vol. C-40, pp. 743-763, June 1991.
18. K. Chakrabarty and J. P. Hayes, "Cumulative balance testing of logic circuits," IEEE Trans. VLSI Syst., vol. 3, pp. 72-83, Mar. 1995.
19. K. Chakrabarty, "Test Response Compaction for Built - In Self Testing," Ph.D. Dissertation, Dept. Computer Science and Engineering, Univ. of Michigan, Ann Arbor, MI, 1995.
20. K. K. Saluja and M. Karpovsky, "Testing computer hardware through compression in space and time," in Proc. Int. Test Conf., 1983, pp. 83-88.
21. Y. Zorian and V. K. Agarwal, "A general scheme to optimize error masking in built-in self testing," in Proc. Int. Symp. Fault-Tolerant Comput., 1986, pp. 410-415.
22. Y. K. Li and J. P. Robinson, "Space compression method with output data modification," IEEE Trans. Comput. Aided Design, vol. 6, pp. 290-294, Mar. 1987.
23. S. M. Reddy, K. K. Saluja, and M. G. Karpovsky, "Data compression technique for test responses," IEEE Trans. Comput., vol. C-37, pp. 1151-1156, Sept. 1988.
24. M. Karpovsky and P. Nagvajara, "Optimal robust compression of test responses," IEEE Trans. Comput., vol. C-39, pp. 138-141, Jan. 1990.
25. W.-B. Jone and S. R. Das, "Space compression method for built-in self-testing of VLSI circuits," Int. J. Comput. Aided VLSI Design, vol. 3, pp. 309-322, Sept. 1991.
26. S. R. Das, H. T. Ho, W. B. Jone, and A. R. Nayak, "An improved output compaction technique for built-in self-test in VLSI circuits," in Proc. Int. Conf. VLSI Design, 1994, pp. 403-407.
27. K. Chakrabarty and J. P. Hayes, "Efficient test response compression for multiple-output circuits," in Proc. Int. Test Conf., 1994, pp. 501-510.
28. J. Savir, "Reducing the MISR size," IEEE Trans. Comput., vol. C-45, pp. 930-935, Aug. 1996.
29. S. R. Das, E. M. Petriu, T. Barakat, M. H. Assaf, and A. R. Nayak, "Space compaction under generalized mergeability," IEEE Trans. Instrum. Meas., vol. 47, pp. 1283-1293, Oct. 1998.
30. S. R. Das, T. F. Barakat, E. M. Petriu, M. H. Assaf, and K. Chakrabarty, "Space compression revisited," IEEE Trans. Instrum. Meas., vol. 49, pp. 690-705, June 2000.
31. J. Y. Liang, "Response Data Compaction in BIST Under Generalized Mergeability Based on Switching Theory Formulation and Utilizing a New Measure of Failure Probability," M.A.Sc. Thesis, School of Information Technology and Engineering, Univ. of Ottawa, Ottawa, ON, Canada, Sept. 2000.
32. S. R. Das, C. V. Ramamoorthy, M. H. Assaf, E. M. Petriu, and W.-B. Jone, "Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities," IEEE Trans. Instrum. Meas., vol. 50, pp. 1725-1747, Dec. 2001.
33. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. New York: W. H. Freeman, 1979.
34. H. K. Lee and D. S. Ha, "On the Generation of Test Patterns for Combinatorial Circuits," Dept. Electrical Engineering, Virginia Polytechnic Institute and State Univ., Blacksburg, VA, Tech. Rep. 12-93, 1993.
35. ____, "An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation," in Proc. Int. Test Conf., 1991, pp. 946-955.
36. I. Pomeranz, L. N. Reddy, and S. M. Reddy, "COMPACTEST: A method to generate compact test sets for combinatorial circuits," in Proc. Int. Test Conf., 1991, pp. 194-203.
37. M. Şahinoǧlu, C. Bayrak, and T. Cummings, "High assurance software testing in business and DoD," Trans. Soc. Design Process Sci., vol. 6, pp. 107-114, June 2002.