A low power SOI adder using reduced-swing charge recycling circuits

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 459, Issue , 2001, Pages 316-317

  Inoue, Atsuki ^a   Oklobdzija, Vojin G ^b   Walker, William W ^a   Kai, Mutsuaki ^c   Izawa, Tetsuo ^c  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b Integration Corporation   (United States)

^c FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); LOGIC CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

LOW POWER ADDERS;

ADDERS;

EID: 0035054772     PISSN: 01936530     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISSCC.2001.912654     Document Type: Article

References (4)

1. 2 2-D DCT macrocell using sense amplifying pipeline flip-flop scheme
2. An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's
3. A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
4. An 8.5-ns 112-b transmission gate adder with a conflict-free bypass-transistor logic circuits