The design of low power multiple-valued logic encoder and decoder circuits

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1999, Pages 1623-1626

  Thoidis, I M ^a   Soudris, D ^a   Karafyllidis, I ^a   Thanailakis, A ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; LOW POWER ELECTRONICS; MANY VALUED LOGICS; SPICE;

DECODER CIRCUITS; LOW-POWER DISSIPATION; MULTIPLE VALUED LOGIC; QUATERNARY LOGIC; STATIC POWER CONSUMPTION; STEADY-STATE OPERATION; TRANSISTOR COUNT; VOLTAGE-MODE CIRCUITS;

LOGIC CIRCUITS;

EID: 0005030320     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1999.814484     Document Type: Conference Paper

References (5)

1. K.W. Current, "Current-Mode Multiple-Valued Logic Circuits", lEEE Journal of Solid State Circuits, vol. 29, no. 2, pp. 95-107, Feb. 1994.
2. N.R. Shanbhag, D. Nagchoudhuri, R.E. Sirerd and G.S. Visweswaran, "Quaternary logic circuits in 2-pm CMOS technology", IEEE Journal of Solid-state Circuits, 25 (3), pp.790-799, 1990.
3. I. Thoidis, D. Soudris, I. Karafyllidis, S . Christoforidis and A. Thanailakis, "Quaternary voltage-mode CMOS circuits for Multiple-valued Logic", IEE Proc.-Circuits, Devices, and Systems, vol. 145, pp.71-77, April 1998.
4. I. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis and T. Stouraitis, "Methodology for Designing Multiple-Valued Logic Voltage-Mode Circuits", Proc. of Int. Symp. on Circuits and Systems (ISCAS), vol. 11, Monterey, California, USA, June 1-3, 1998, pp. 125-128.
5. J. L. Mangin and K. W. Current, "Characteristics of prototype CMOS quaternary logic encoder-decoder circuits", IEEE Transactions on Computer, C-35 (2), pp. 157-161, February 1986.