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Volumn 4700, Issue , 2002, Pages 17-28

A novel scheme for a higher bandwidth sensor readout

Author keywords

Floating gate MOSFET; Quaternary logic; Sensor readout

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; BINARY CODES; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC POTENTIAL; MICROELECTROMECHANICAL DEVICES; MOSFET DEVICES; VLSI CIRCUITS;

EID: 0036028894     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.475050     Document Type: Conference Paper
Times cited : (6)

References (10)
  • 2
    • 0034135540 scopus 로고    scopus 로고
    • Readout electronics scheme in CMOS technology for integration with analog outputs from integrated smart sensors
    • February
    • A. Srivastava, S.V. Prasanna and P.K. Ajmera, "Readout electronics scheme in CMOS technology for integration with analog outputs from integrated smart sensors," J. of Intelligent Material Systems and Structures, 11, pp. 116-124, February 2000.
    • (2000) J. of Intelligent Material Systems and Structures , vol.11 , pp. 116-124
    • Srivastava, A.1    Prasanna, S.V.2    Ajmera, P.K.3
  • 4
    • 0022665606 scopus 로고
    • Characteristics of prototype CMOS quaternary logic encoder-decoder circuits
    • February
    • J.L. Mangin and K.W. Current, "Characteristics of prototype CMOS quaternary logic encoder-decoder circuits," IEEE Trans. on Computers, C-35, pp. 157-161, February 1986.
    • (1986) IEEE Trans. on Computers , vol.C-35 , pp. 157-161
    • Mangin, J.L.1    Current, K.W.2
  • 7
    • 84954088099 scopus 로고
    • An intelligent MOS transistor featuring gate-level weighted sum and threshold operations
    • T. Shibata and T. Ohmi, "An intelligent MOS transistor featuring gate-level weighted sum and threshold operations," IEDM Tech. Dig., pp. 919-922, 1991.
    • (1991) IEDM Tech. Dig. , pp. 919-922
    • Shibata, T.1    Ohmi, T.2
  • 8
    • 27944492851 scopus 로고
    • A functional MOS transistor featuring gate-level weighted sum and threshold operations
    • June
    • T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations," IEEE Transactions on Electron devices, 39, pp. 1444-1455, June 1992.
    • (1992) IEEE Transactions on Electron devices , vol.39 , pp. 1444-1455
    • Shibata, T.1    Ohmi, T.2
  • 9
    • 0033731346 scopus 로고    scopus 로고
    • On the design robustness of threshold logic gates using multi-input floating gate MOS transistors
    • June 2000, June
    • A. Luck, S. Jung, R. Brederlow, R. Thewes, K. Goser and W. Weber, "On the design robustness of threshold logic gates using multi-input floating gate MOS transistors," IEEE Transactions on Electron Devices, 47, June 2000, pp. 1231-1239, June 2000.
    • (2000) IEEE Transactions on Electron Devices , vol.47 , pp. 1231-1239
    • Luck, A.1    Jung, S.2    Brederlow, R.3    Thewes, R.4    Goser, K.5    Weber, W.6
  • 10


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.