On the micro-architectural impact of clock distribution using multiple PLLs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 214-220

  Saint Laurent, Martin ^a   Swaminathant, Madhavan ^b   Meindl, James D ^b  

^a INTEL CORPORATION   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; PHASE LOCKED LOOPS; SYNCHRONIZATION;

CLOCK DISTRIBUTION NETWORKS;

TIMING CIRCUITS;

EID: 0035183671     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.955031     Document Type: Article

References (11)

1. Clock generation and distribution for the first IA-64 microprocessor
2. Active GHz clock network using distributed PLLs
3. A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators
4. A multi-PLL clock distribution architecture for gigascale integration
5. A digitally adjustable resistor for path delay characterization in high-frequency microprocessors
6. A 2-1600-MHz CMOS clock recovery PLL with low-vdd capability
7. A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz
8. Distributed synchronous clocking
9. Feedback techniques for skew and jitter compensation in high-frequency clock distribution networks
10. The design and analysis of the clock distribution network for a 1.2GHz Alpha microprocessor
11. An adaptive digital deskewing circuit for clock distribution networks