SoC implementation issues for synthesizable embedded programmable logic cores

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 45-48

  Wu, James C H ^a   Aken'Ova, Victor ^a   Wilton, Steven J E ^a   Saleh, Resve ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK SYNTHESIS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES;

CLOCK TREE SYNTHESIS; PROGRAMMABLE LOGIC CORES; SYSTEM ON CHIP;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0242527314     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. J. Greenbaum, "Reconfigurable Logic in SoC Systems", Proceedings of the 2002 Custom Integrated Circuits Conference, pp. 5-8.
2. S.J.E. Wilton, R. Saleh, "Programmable Logic IP Cores in SoC Design: Opportunities and Challenges", Proceedings of the 2001 Custom Integrated Circuits Conference, pp. 63-66.
3. Actel Corp, "VariCore Embedded Programmable Gate Array Core (EPGA) 0.18μm Family", Datasheet, December 2001.
4. Leopard Logic Inc, "HyperBlox FP Embedded FPGA Cores", Product Brief, 2002.
5. M2000, Inc, "M2000 FLEXEOStm Configurable IP Core", http://www.m2000.fr.
6. eASCI, "eASIC 0.13μm Core", http://www.easic.com/products/easicore013.html.
7. M. Borgatti, F. Lertora, B. Foret, L. Cali, "A Reconfigurable System featuring Dynamically Extensible Embedded Microprocessor, FPGA, and Customisable I/O", IEEE Journal of Solid-State Circuits, vol. 38, no. 3, March 2003, pp. 521-529.
8. T. Vaida, "PLC Advanced Technology Demonstrator TestChipB", Proceedings of the 2001 Custom Integrated Circuits Conference, May 2001, pp. 67-70.
9. N. Kafafi, K. Bozman, S.J.E. Wilton, "Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores", Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, Feb 2003, pp. 1-9.
10. Mohsen Nahvi, Andre Ivanov, "A Packet Switching Communication-Based Test Access Mechanism for System Chips," in Proceedings of the IEEE European Test Workshop, 2001, pp. 81-86.