A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 3, 2003, Pages 521-529

  Borgatti, Michele ^a   Lertora, Francesco ^a   Forêt, Benoit ^b   Calí, Lorenzo ^a  

^a STMICROELECTRONICS   (Italy)

^b STMICROELECTRONICS   (France)

Author keywords

Application specific integrated circuits (ASICs); Digital signal processors; Field programmable gate arrays (FPGAs); Integrated circuit design; Multimedia computing; Reconfigurable architectures

Indexed keywords

CMOS INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SEMICONDUCTING SILICON;

MULTIMEDIA COMPUTING; PROGRAMMABLE LOGIC; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE SYSTEM; SYSTEM ON CHIP DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0037344580     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.808288     Document Type: Article

References (13)

1. R. E. Gonzalez, "Xtensa: A configurable and extensible processor," IEEE Micro, vol. 20, pp. 60-70, Mar./Apr. 2000.
2. M2000 Flexeos Family Technical Manual. [Online]. Available: http://www.m2000.fr.
3. AMBA™ Specification Rev. 2.0, ARM Ltd., 1999.
4. I. Bolsens, H. De Man, B. Lin, C. Van Rompaey, S. Vercauteren, and D. Verkest, "Hardware/software co-design of digital telecommunication systems," Proc. IEEE, vol. 85, pp. 391-418, Mar. 1997.
5. D. Maio and D. Maltoni, "Real-time face location on gray-scale static images," Pattern Recognit., vol. 33, no. 9, pp. 1525-1539, Sept. 2000.
6. O. De Vel and S. Aebrhard, "Line-based face recognition under varying pose," IEEE Trans. Pattern Anal. Machine Intell., vol. 21, pp. 1081-1088, Oct. 1999.
7. S. Hauck, "The roles of FPGAs in reprogrammable systems," Proc. IEEE, vol. 86, pp. 615-638, Apr. 1998.
8. E. Sanchez, M. Sipper, J.-O. Haenni, J.-L. Beuchat, A. Stauffer, and A. Perez-Uribe, "Static and dynamic configurable systems," IEEE Trans. Comput., vol. 48, pp. 556-564, June 1999.
9. A. DeHon, "DPGA-coupled microprocessors: Commodity ICs for the early 21st century," in Proc. IEEE Workshop FPGAs for Custom Computing Machines, Napa Valley, CA, Apr. 1994, pp. 31-39.
10. M. J. Wirthlin and B. L. Hutchings, "A dynamic instruction set computer," in Proc. IEEE Symp. FPGAs for Custom Computing Machines, Napa Valley, CA, Apr. 1995, pp. 122-128.
11. R. D. Wittig and P. Chow, "OneChip: An FPGA processor with reconfigurable logic," in Proc. IEEE Symp. FPGAs for Custom Computing Machines, Napa Valley, CA, Apr. 1996, pp. 126-135.
12. J. R. Hauser and J. Wawrzynek, "Garp: A MIPS processor with a reconfigurable coprocessor," in Proc. IEEE Symp. FPGAs for Custom Computing Machines, Napa Valley, CA, Apr. 1997, pp. 12-21.
13. "Cover: Configurable computing," IEEE Comput., vol. 33, pp. 39-77, Apr. 2000.