PLL design for a 500 MB/s interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1993, Pages 160-161

  Horowitz, M ^a,b   Chan, A ^a,b   Cobrunson, J ^a,b   Gasbarro, J ^a,b   Lee, T ^a,b   Leung, W ^a,b   Richardson, W ^a,b   Thrush, T ^a,b   Fujii, Y ^a,b  

^a RAMBUS INC   (United States)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; LOCKS (FASTENERS); OSCILLISTORS; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK FREQUENCY; CLOCKING SCHEMES; DIFFERENTIAL RINGS; EXTERNAL SIGNALS; HIGH DATA RATE; INTERNAL CLOCK; PHASE/FREQUENCY DETECTOR; SENDER AND RECEIVERS;

CLOCKS;

EID: 84986332214     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1993.280015     Document Type: Conference Paper

References (3)

1. Kushiyams et al., "500 MByte/sec Data Rate 012 Khits x 9 DRAM Using a Navel 110 Interface", Syon. an VLSI Circuits, Digest af Technical Papers, pp. 66-67, June 1992.
2. Yeung, I. et al A PLL Clock Generator with 5 ta 110MHz Lock Range for Microprocessors", 155CC DIGEST OF TECHNICAL PAPERS, p. 50, Feb. 1992.
3. The Fujitsu MB614953.