A Massively Parallel Architecture for Self-Organizing Feature Maps

IEEE Transactions on Neural Networks

Volumn 14, Issue 5, 2003, Pages 1110-1121

  Porrmann, Mario ^a   Witkowski, Ulf ^a   Rückert, Ulrich ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

Hardware accelerator; Self organizing feature maps; Very large scale integration (VLSI) design

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; INTERNET; LOGIC GATES; MICROELECTRONICS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

ETHERNET; HARDWARE ACCELERATORS;

SELF ORGANIZING MAPS;

EID: 0242443334     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2003.816368     Document Type: Article

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