메뉴 건너뛰기




Volumn 1240 LNCS, Issue , 1997, Pages 688-713

Digital connectionist hardware: Current problems and future challenges

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

EID: 84902143688     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0032529     Document Type: Conference Paper
Times cited : (12)

References (45)
  • 2
    • 84902195159 scopus 로고
    • Programmable VLSI array processor for neural networks and matrixbased signal processing - user description
    • Munich, Oct. Version 1.3
    • N. Briils. Programmable VLSI array processor for neural networks and matrixbased signal processing - User description. Technical report, Siemens AG, Corporate Research and Development Division, Munich, Oct. 1993. Version 1.3.
    • (1993) Technical Report, Siemens AG, Corporate Research and Development Division
    • Briils, N.1
  • 7
    • 0029256348 scopus 로고
    • Vertical processing systems: A survey
    • Feb
    • Y. I. Fet. Vertical processing systems: A survey. IEEE Micro, 15(1):65-75, Feb. 1995.
    • (1995) IEEE Micro , vol.15 , Issue.1 , pp. 65-75
    • Fet, Y.I.1
  • 10
    • 0038036720 scopus 로고
    • A massively-parallel simd processor for neural network and machine vision applications
    • J. D. Cowan, G. Tesauro, and J. Alspector, editors, San Mateo, Calif., Morgan Kaufmann
    • M. A. Glover and W. T. Miller,. A massively-parallel SIMD processor for neural network and machine vision applications. In J. D. Cowan, G. Tesauro, and J. Alspector, editors, Advances in Neural Information Processing Systems, volume 6, pages 843-49, San Mateo, Calif., 1994. Morgan Kaufmann.
    • (1994) Advances in Neural Information Processing Systems , vol.6 , pp. 843-849
    • Glover, M.A.1    Miller, W.T.2
  • 12
    • 0007961183 scopus 로고
    • A highly parallel digital architecture for neural network emulation
    • J. G. Delgado-Frias and W. R. Moore, editors, chapter 5.1, Plenum Press, New York
    • D. Hammerstrom. A highly parallel digital architecture for neural network emulation. In J. G. Delgado-Frias and W. R. Moore, editors, VLSI for Artificial Intelligence and Neural Networks, chapter 5.1, pages 357-66. Plenum Press, New York, 1991.
    • (1991) VLSI for Artificial Intelligence and Neural Networks , pp. 357-366
    • Hammerstrom, D.1
  • 14
    • 0027557033 scopus 로고
    • Finite precision error analysis of neural network hardware implementations
    • Mar
    • J. L. Holt and J.-N. Hwang. Finite precision error analysis of neural network hardware implementations. IEEE Transactions on Computers, 42(3):281-90, Mar. 1993.
    • (1993) IEEE Transactions on Computers , vol.42 , Issue.3 , pp. 281-290
    • Holt, J.L.1    Hwang, J.-N.2
  • 15
    • 84902161164 scopus 로고
    • (Preliminary), Nov. Version 2.1
    • IBM. ZISC036 Data Book (Preliminary), Nov. 1994. Version 2.1.
    • (1994) IBM. ZISC036 Data Book
  • 16
    • 0030213156 scopus 로고    scopus 로고
    • Special-purpose digital hardware for neural networks: An architectural survey
    • P. Ienne, T. Cornu, and G. Kuhn. Special-purpose digital hardware for neural networks: An architectural survey. Journal of VLSI Signal Processing, 13(1):5-25, 1996.
    • (1996) Journal of VLSI Signal Processing , vol.13 , Issue.1 , pp. 5-25
    • Ienne, P.1    Cornu, T.2    Kuhn, G.3
  • 17
    • 0031100792 scopus 로고    scopus 로고
    • Modified self-organizing feature map algorithms for efficient digital hardware implementation
    • Mar. To appear
    • P. Ienne, P. Thiran, and N. Vassilas. Modified self-organizing feature map algorithms for efficient digital hardware implementation. IEEE Transactions on Neural Networks, 8(2), Mar. 1997. To appear.
    • (1997) IEEE Transactions on Neural Networks , vol.8 , Issue.2
    • Ienne, P.1    Thiran, P.2    Vassilas, N.3
  • 18
    • 0029288205 scopus 로고
    • Genes iv: A bit-serial processing element for a multi-model neural-network accelerator
    • Apr
    • P. Ienne and M. A. Viredaz. GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. Journal of VLSI Signal Processing, 9(3):257-73, Apr. 1995.
    • (1995) Journal of VLSI Signal Processing , vol.9 , Issue.3 , pp. 257-273
    • Ienne, P.1    Viredaz, M.A.2
  • 20
    • 0000293377 scopus 로고
    • Backpropagation learning for multilayer feed-forward neural networks using the conjugate gradient method
    • E. M. Johansson, F. U. Dowla, and D. M. Goodman. Backpropagation learning for multilayer feed-forward neural networks using the conjugate gradient method. International Journal of Neural Systems, 2(4):291-301, 1992.
    • (1992) International Journal of Neural Systems , vol.2 , Issue.4 , pp. 291-301
    • Johansson, E.M.1    Dowla, F.U.2    Goodman, D.M.3
  • 22
    • 0026866931 scopus 로고
    • Functional abilities of a stochastic logic neural network
    • May
    • Y. Kondo and Y. Sawada. Functional abilities of a stochastic logic neural network. IEEE Transactions on Neural Networks, 3(3):434-43, May 1992.
    • (1992) IEEE Transactions on Neural Networks , vol.3 , Issue.3 , pp. 434-443
    • Kondo, Y.1    Sawada, Y.2
  • 23
    • 2142734507 scopus 로고
    • Survey and current status of neural network hardware
    • F. Fogelman- Soulie and P. Gallinari, editors, Paris, Oct
    • A. Konig. Survey and current status of neural network hardware. In F. Fogelman- Soulie and P. Gallinari, editors, Proceedings of the International Conference on Artificial Neural Networks, pages 391-410, Paris, Oct. 1995.
    • (1995) Proceedings of the International Conference on Artificial Neural Networks , pp. 391-410
    • Konig, A.1
  • 27
    • 0010582394 scopus 로고
    • Back propagation implementation on the adaptive solutions neurocomputer chip
    • D. S. Touretzky, editor, San Mateo, Calif., Morgan Kaufmann
    • H. McCartor. Back propagation implementation on the Adaptive Solutions neurocomputer chip. In D. S. Touretzky, editor, Advances in Neural Information Processing Systems, volume 3, San Mateo, Calif., 1991. Morgan Kaufmann.
    • (1991) Advances in Neural Information Processing Systems , vol.3
    • McCartor, H.1
  • 28
    • 0010582396 scopus 로고
    • Floating-point simd neurocomputer array processor
    • K. W. Prztula and V. K. Prasanna, editors, Prentice Hall, New York
    • R. W. Means and L. Lisenbee. Floating-point SIMD neurocomputer array processor. In K. W. Prztula and V. K. Prasanna, editors, Parallel Implementations of Neural Networks. Prentice Hall, New York, 1993.
    • (1993) Parallel Implementations of Neural Networks
    • Means, R.W.1    Lisenbee, L.2
  • 34
    • 0004042460 scopus 로고
    • PROBEN1 - A set of neural network benchmark problems and benchmarking rules
    • Sept.
    • L. Prechelt. PROBEN1 - A set of neural network benchmark problems and benchmarking rules. Technical Report 21/94, Universitat Karlsruhe, Sept. 1994.
    • (1994) Technical Report 21/94, Universitat Karlsruhe
    • Prechelt, L.1
  • 35
    • 0026830166 scopus 로고
    • SYNAPSE - A neurocomputer that synthesizes neural algorithms on a parallel systolic engine
    • Mar
    • U. Raznacher. SYNAPSE - A neurocomputer that synthesizes neural algorithms on a parallel systolic engine. Journal of Parallel and Distributed Computing, 14(3):306-18, Mar. 1992.
    • (1992) Journal of Parallel and Distributed Computing , vol.14 , Issue.3 , pp. 306-318
    • Raznacher, U.1
  • 37
    • 0000383868 scopus 로고
    • Parallel networks that learn to pronounce english text
    • T. J. Sejnowski and C. R. Rosenberg. Parallel networks that learn to pronounce english text. Complex Systems, 1:145-68, 1987.
    • (1987) Complex Systems , vol.1 , pp. 145-168
    • Sejnowski, T.J.1    Rosenberg, C.R.2
  • 41
    • 0028425063 scopus 로고
    • Quantization effects in digitally behaving circuit implementations of kohonen networks
    • May
    • P. Thiran, V. Peiris, P. Heim, and B. Hochet. Quantization effects in digitally behaving circuit implementations of Kohonen networks. IEEE Transactions on Neural Networks, 5 (3):450-58, May 1994.
    • (1994) IEEE Transactions on Neural Networks , vol.5 , Issue.3 , pp. 450-458
    • Thiran, P.1    Peiris, V.2    Heim, P.3    Hochet, B.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.