-
2
-
-
84902195159
-
Programmable VLSI array processor for neural networks and matrixbased signal processing - user description
-
Munich, Oct. Version 1.3
-
N. Briils. Programmable VLSI array processor for neural networks and matrixbased signal processing - User description. Technical report, Siemens AG, Corporate Research and Development Division, Munich, Oct. 1993. Version 1.3.
-
(1993)
Technical Report, Siemens AG, Corporate Research and Development Division
-
-
Briils, N.1
-
3
-
-
0000444865
-
Learning probabilistic RAM nets using VLSI structures
-
Dec.
-
T. G. Clarkson, D. Gorse, J. G. Taylor, and C. K. Ng. Learning probabilistic RAM nets using VLSI structures. IEEE Transactions on Computers, 41(12):1552-61, Dec. 1992.
-
(1992)
IEEE Transactions on Computers
, vol.41
, Issue.12
, pp. 1552-1561
-
-
Clarkson, T.G.1
Gorse, D.2
Taylor, J.G.3
Ng, C.K.4
-
7
-
-
0029256348
-
Vertical processing systems: A survey
-
Feb
-
Y. I. Fet. Vertical processing systems: A survey. IEEE Micro, 15(1):65-75, Feb. 1995.
-
(1995)
IEEE Micro
, vol.15
, Issue.1
, pp. 65-75
-
-
Fet, Y.I.1
-
8
-
-
0027631483
-
Development and fabrication of digital neural network wsis
-
July
-
M. Fujita, Y. Kobayashi, K. Shiozawa, T. Takahashi, F. Mizuno, H. Hayakawa, M. Kato, S. Mori, T. Kase, and M. Yaznada. Development and fabrication of digital neural network WSIs. IEICE Transactions on Electronics, 76 (7):1182-90, July 1993.
-
(1993)
IEICE Transactions on Electronics
, vol.76
, Issue.7
, pp. 1182-1190
-
-
Fujita, M.1
Kobayashi, Y.2
Shiozawa, K.3
Takahashi, T.4
Mizuno, F.5
Hayakawa, H.6
Kato, M.7
Mori, S.8
Kase, T.9
Yaznada, M.10
-
10
-
-
0038036720
-
A massively-parallel simd processor for neural network and machine vision applications
-
J. D. Cowan, G. Tesauro, and J. Alspector, editors, San Mateo, Calif., Morgan Kaufmann
-
M. A. Glover and W. T. Miller,. A massively-parallel SIMD processor for neural network and machine vision applications. In J. D. Cowan, G. Tesauro, and J. Alspector, editors, Advances in Neural Information Processing Systems, volume 6, pages 843-49, San Mateo, Calif., 1994. Morgan Kaufmann.
-
(1994)
Advances in Neural Information Processing Systems
, vol.6
, pp. 843-849
-
-
Glover, M.A.1
Miller, W.T.2
-
11
-
-
0010614351
-
An II-Million transistor neural network execution engine
-
M. Griffin, G. Tahara, K. Knorpp, and B. Riley. An II-million transistor neural network execution engine. In IEEE International Conference on Solid-State Circuits, pages 180-81, 1991.
-
(1991)
IEEE International Conference on Solid-State Circuits
, pp. 180-181
-
-
Griffin, M.1
Tahara, G.2
Knorpp, K.3
Riley, B.4
-
12
-
-
0007961183
-
A highly parallel digital architecture for neural network emulation
-
J. G. Delgado-Frias and W. R. Moore, editors, chapter 5.1, Plenum Press, New York
-
D. Hammerstrom. A highly parallel digital architecture for neural network emulation. In J. G. Delgado-Frias and W. R. Moore, editors, VLSI for Artificial Intelligence and Neural Networks, chapter 5.1, pages 357-66. Plenum Press, New York, 1991.
-
(1991)
VLSI for Artificial Intelligence and Neural Networks
, pp. 357-366
-
-
Hammerstrom, D.1
-
13
-
-
0013284402
-
-
PhD thesis, Leiden University, Leiden, The Netherlands, Draft of Chapter 3 available
-
J. N.H. Heemskerk. Neurocomputers for Brain-Style Processing Design, Implementation and Application. PhD thesis, Leiden University, Leiden, The Netherlands, 1995. Draft of Chapter 3 available at URL ftp://ftp.dcs.shef.ac.u- k/home/janh/neurhard, ps.gz.
-
(1995)
Neurocomputers for Brain-Style Processing Design, Implementation and Application
-
-
Heemskerk, J.N.H.1
-
14
-
-
0027557033
-
Finite precision error analysis of neural network hardware implementations
-
Mar
-
J. L. Holt and J.-N. Hwang. Finite precision error analysis of neural network hardware implementations. IEEE Transactions on Computers, 42(3):281-90, Mar. 1993.
-
(1993)
IEEE Transactions on Computers
, vol.42
, Issue.3
, pp. 281-290
-
-
Holt, J.L.1
Hwang, J.-N.2
-
15
-
-
84902161164
-
-
(Preliminary), Nov. Version 2.1
-
IBM. ZISC036 Data Book (Preliminary), Nov. 1994. Version 2.1.
-
(1994)
IBM. ZISC036 Data Book
-
-
-
16
-
-
0030213156
-
Special-purpose digital hardware for neural networks: An architectural survey
-
P. Ienne, T. Cornu, and G. Kuhn. Special-purpose digital hardware for neural networks: An architectural survey. Journal of VLSI Signal Processing, 13(1):5-25, 1996.
-
(1996)
Journal of VLSI Signal Processing
, vol.13
, Issue.1
, pp. 5-25
-
-
Ienne, P.1
Cornu, T.2
Kuhn, G.3
-
17
-
-
0031100792
-
Modified self-organizing feature map algorithms for efficient digital hardware implementation
-
Mar. To appear
-
P. Ienne, P. Thiran, and N. Vassilas. Modified self-organizing feature map algorithms for efficient digital hardware implementation. IEEE Transactions on Neural Networks, 8(2), Mar. 1997. To appear.
-
(1997)
IEEE Transactions on Neural Networks
, vol.8
, Issue.2
-
-
Ienne, P.1
Thiran, P.2
Vassilas, N.3
-
18
-
-
0029288205
-
Genes iv: A bit-serial processing element for a multi-model neural-network accelerator
-
Apr
-
P. Ienne and M. A. Viredaz. GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. Journal of VLSI Signal Processing, 9(3):257-73, Apr. 1995.
-
(1995)
Journal of VLSI Signal Processing
, vol.9
, Issue.3
, pp. 257-273
-
-
Ienne, P.1
Viredaz, M.A.2
-
20
-
-
0000293377
-
Backpropagation learning for multilayer feed-forward neural networks using the conjugate gradient method
-
E. M. Johansson, F. U. Dowla, and D. M. Goodman. Backpropagation learning for multilayer feed-forward neural networks using the conjugate gradient method. International Journal of Neural Systems, 2(4):291-301, 1992.
-
(1992)
International Journal of Neural Systems
, vol.2
, Issue.4
, pp. 291-301
-
-
Johansson, E.M.1
Dowla, F.U.2
Goodman, D.M.3
-
21
-
-
17444382590
-
On-chip backpropagation training using parallel stochastic bit streams
-
Lausanne, Feb
-
K. Kollmann, K.-R. Riemschneider, and H. C. Zeidler. On-chip backpropagation training using parallel stochastic bit streams. In Proceedings of the Fifth International Conference on Microeleetronics for Neural Networks and Fuzzy Systems, pages 149-56, Lausanne, Feb. 1996.
-
(1996)
Proceedings of the Fifth International Conference on Microeleetronics for Neural Networks and Fuzzy Systems
, pp. 149-156
-
-
Kollmann, K.1
Riemschneider, K.-R.2
Zeidler, H.C.3
-
22
-
-
0026866931
-
Functional abilities of a stochastic logic neural network
-
May
-
Y. Kondo and Y. Sawada. Functional abilities of a stochastic logic neural network. IEEE Transactions on Neural Networks, 3(3):434-43, May 1992.
-
(1992)
IEEE Transactions on Neural Networks
, vol.3
, Issue.3
, pp. 434-443
-
-
Kondo, Y.1
Sawada, Y.2
-
23
-
-
2142734507
-
Survey and current status of neural network hardware
-
F. Fogelman- Soulie and P. Gallinari, editors, Paris, Oct
-
A. Konig. Survey and current status of neural network hardware. In F. Fogelman- Soulie and P. Gallinari, editors, Proceedings of the International Conference on Artificial Neural Networks, pages 391-410, Paris, Oct. 1995.
-
(1995)
Proceedings of the International Conference on Artificial Neural Networks
, pp. 391-410
-
-
Konig, A.1
-
25
-
-
0027206090
-
Fast neural networks without multipliers
-
Jan
-
M. Marchesi, G. Orlandi, and F. Piazza. Fast neural networks without multipliers. IEEE Transactions on Neural Networks, 4(1):53-62, Jan. 1993.
-
(1993)
IEEE Transactions on Neural Networks
, vol.4
, Issue.1
, pp. 53-62
-
-
Marchesi, M.1
Orlandi, G.2
Piazza, F.3
-
26
-
-
0026869642
-
Lneuro 1.0: A piece of hardware lego for building neural network systems
-
May
-
N. Mauduit, M. Durauton, J. Gobert, and J. A. Sirat. Lneuro 1.0: A piece of hardware LEGO for building neural network systems. IEEE Transactions on Neural Networks, 3(3):414-22, May 1992.
-
(1992)
IEEE Transactions on Neural Networks
, vol.3
, Issue.3
, pp. 414-422
-
-
Mauduit, N.1
Durauton, M.2
Gobert, J.3
Sirat, J.A.4
-
27
-
-
0010582394
-
Back propagation implementation on the adaptive solutions neurocomputer chip
-
D. S. Touretzky, editor, San Mateo, Calif., Morgan Kaufmann
-
H. McCartor. Back propagation implementation on the Adaptive Solutions neurocomputer chip. In D. S. Touretzky, editor, Advances in Neural Information Processing Systems, volume 3, San Mateo, Calif., 1991. Morgan Kaufmann.
-
(1991)
Advances in Neural Information Processing Systems
, vol.3
-
-
McCartor, H.1
-
28
-
-
0010582396
-
Floating-point simd neurocomputer array processor
-
K. W. Prztula and V. K. Prasanna, editors, Prentice Hall, New York
-
R. W. Means and L. Lisenbee. Floating-point SIMD neurocomputer array processor. In K. W. Prztula and V. K. Prasanna, editors, Parallel Implementations of Neural Networks. Prentice Hall, New York, 1993.
-
(1993)
Parallel Implementations of Neural Networks
-
-
Means, R.W.1
Lisenbee, L.2
-
29
-
-
0026824973
-
The ring array processor: A multiprocessing peripheral for connectionist applications
-
Mar
-
N. Morgan, J. Beck, P. Kohn, J. Bilmes, E. Allman, and J. Beer. The Ring Array Processor: A multiprocessing peripheral for connectionist applications. Journal of Parallel and Distributed Computing, 14(3):248-59, Mar. 1992.
-
(1992)
Journal of Parallel and Distributed Computing
, vol.14
, Issue.3
, pp. 248-259
-
-
Morgan, N.1
Beck, J.2
Kohn, P.3
Bilmes, J.4
Allman, E.5
Beer, J.6
-
30
-
-
0029196050
-
Fast neural net simulation with a DSP processor array
-
Jan
-
U. A. Miiller, A. Gunzinger, and W. Guggenbiihl. Fast neural net simulation with a DSP processor array. IEEE Transactions on Neural Networks, 6(1):203-13, Jan. 1995.
-
(1995)
IEEE Transactions on Neural Networks
, vol.6
, Issue.1
, pp. 203-213
-
-
Miiller, U.A.1
Gunzinger, A.2
Guggenbiihl, W.3
-
32
-
-
0027883538
-
A digital neural network vlsi with on-chip learning using stochastic pulse encoding
-
Nagoya, Japan, Oct
-
S. Oteki, A. Hashimoto, T. Furuta, T. Watanabe, D. G. Stork, and H. Eguchi. A digital neural network VLSI with on-chip learning using stochastic pulse encoding. In Proceedings of the International Joint Conference on Neural Networks, volume 3, pages 3039-45, Nagoya, Japan, Oct. 1993.
-
(1993)
Proceedings of the International Joint Conference on Neural Networks
, vol.3
, pp. 3039-3045
-
-
Oteki, S.1
Hashimoto, A.2
Furuta, T.3
Watanabe, T.4
Stork, D.G.5
Eguchi, H.6
-
33
-
-
0027811871
-
A radial basis function neural network with on-chip learning
-
Nagoya, Japan, Oct
-
C. Park, K. Buckmann, J. Diamond, U. Santoni, S.-C. The, M. Holler, M. Glier, C. L. Scofield, and L. Nunez. A radial basis function neural network with on-chip learning. In Proceedings of the International Joint Conference on Neural Networks, volume 3, pages 3035-38, Nagoya, Japan, Oct. 1993.
-
(1993)
Proceedings of the International Joint Conference on Neural Networks
, vol.3
, pp. 3035-3038
-
-
Park, C.1
Buckmann, K.2
Diamond, J.3
Santoni, U.4
The, S.-C.5
Holler, M.6
Glier, M.7
Scofield, C.L.8
Nunez, L.9
-
34
-
-
0004042460
-
PROBEN1 - A set of neural network benchmark problems and benchmarking rules
-
Sept.
-
L. Prechelt. PROBEN1 - A set of neural network benchmark problems and benchmarking rules. Technical Report 21/94, Universitat Karlsruhe, Sept. 1994.
-
(1994)
Technical Report 21/94, Universitat Karlsruhe
-
-
Prechelt, L.1
-
35
-
-
0026830166
-
SYNAPSE - A neurocomputer that synthesizes neural algorithms on a parallel systolic engine
-
Mar
-
U. Raznacher. SYNAPSE - A neurocomputer that synthesizes neural algorithms on a parallel systolic engine. Journal of Parallel and Distributed Computing, 14(3):306-18, Mar. 1992.
-
(1992)
Journal of Parallel and Distributed Computing
, vol.14
, Issue.3
, pp. 306-318
-
-
Raznacher, U.1
-
36
-
-
0027855197
-
Development of a high-performance general purpose neurocomputer composed of 512 digital neurons
-
Nagoya, Japan, Oct
-
Y. Sato, K. Shibata, M. Asal, M. Ohki, M. Sugie, T. Sakaguchi, M. Hashimoto, and Y. Kuwabara. Development of a high-performance general purpose neurocomputer composed of 512 digital neurons. In Proceedings of the International Joint Conference on Neural Networks, volume 2, pages 1967-70, Nagoya, Japan, Oct. 1993.
-
(1993)
Proceedings of the International Joint Conference on Neural Networks
, vol.2
, pp. 1967-1970
-
-
Sato, Y.1
Shibata, K.2
Asal, M.3
Ohki, M.4
Sugie, M.5
Sakaguchi, T.6
Hashimoto, M.7
Kuwabara, Y.8
-
37
-
-
0000383868
-
Parallel networks that learn to pronounce english text
-
T. J. Sejnowski and C. R. Rosenberg. Parallel networks that learn to pronounce english text. Complex Systems, 1:145-68, 1987.
-
(1987)
Complex Systems
, vol.1
, pp. 145-168
-
-
Sejnowski, T.J.1
Rosenberg, C.R.2
-
38
-
-
84902123805
-
A multiplierless digital neural network
-
Munich
-
L. Spaanenburg, B. Hoeffiinger, S. Neusser, J. A. G. Nijhuis, and A. Siggelkow. A multiplierless digital neural network. In Proceedings of the Second International Conference on Microelectronics for Neural Networks, pages 281-89, Munich, 1991.
-
(1991)
Proceedings of the Second International Conference on Microelectronics for Neural Networks
, pp. 281-289
-
-
Spaanenburg, L.1
Hoeffiinger, B.2
Neusser, S.3
Nijhuis, J.A.G.4
Siggelkow, A.5
-
40
-
-
0003992972
-
The lneuro chip: A digital vlsi with on-chip learning mechanism
-
J. B. Theeten, M. Duranton, N. Mauduit, and J. A. Sirat. The Lneuro chip: A digital VLSI with on-chip learning mechanism. In International Neural Networks Conference, pages 593-96, 1990.
-
(1990)
International Neural Networks Conference
, pp. 593-596
-
-
Theeten, J.B.1
Duranton, M.2
Mauduit, N.3
Sirat, J.A.4
-
41
-
-
0028425063
-
Quantization effects in digitally behaving circuit implementations of kohonen networks
-
May
-
P. Thiran, V. Peiris, P. Heim, and B. Hochet. Quantization effects in digitally behaving circuit implementations of Kohonen networks. IEEE Transactions on Neural Networks, 5 (3):450-58, May 1994.
-
(1994)
IEEE Transactions on Neural Networks
, vol.5
, Issue.3
, pp. 450-458
-
-
Thiran, P.1
Peiris, V.2
Heim, P.3
Hochet, B.4
-
43
-
-
0030106918
-
SPERT-II: A vector m~croprocessor system
-
Mar
-
J. Wawrzynek, K. Asanovid, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan. SPERT-II: A vector m~croprocessor system. Computer, 29(3):79-86, Mar. 1996.
-
(1996)
Computer
, vol.29
, Issue.3
, pp. 79-86
-
-
Wawrzynek, J.1
Asanovid, K.2
Kingsbury, B.3
Beck, J.4
Johnson, D.5
Morgan, N.6
-
44
-
-
0026298228
-
A self-learning neural network composed of 1152 digital neurons in wafer-scale lsis
-
Seattle, Wash. July
-
M. Yasunaga, N. Masuda, M. Yagyu, M. Asai, K. Shibata, M. Ooyama, M. Yamada, T. Sakaguchi, and M. Hashimoto. A self-learning neural network composed of 1152 digital neurons in wafer-scale LSIs. In Proceedings of the International Joint Conference on Neural Networks, pages 1844-49, Seattle, Wash., July 1991.
-
(1991)
Proceedings of the International Joint Conference on Neural Networks
, pp. 1844-1849
-
-
Yasunaga, M.1
Masuda, N.2
Yagyu, M.3
Asai, M.4
Shibata, K.5
Ooyama, M.6
Yamada, M.7
Sakaguchi, T.8
Hashimoto, M.9
-
45
-
-
0025564430
-
Design, fabrication and evaluation of a 5-inch wafer scale neural network lsi composed of 576 digital neurons
-
San Diego, Calif. June
-
M. Yasunaga, N. Masuda, M. Yagyu, M. Asai, M. Yamada, and A. Masaki. Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed of 576 digital neurons. In Proceedings of the International Joint Conference on Neural Networks, volume 2, pages 527-36, San Diego, Calif., June 1990.
-
(1990)
Proceedings of the International Joint Conference on Neural Networks
, vol.2
, pp. 527-536
-
-
Yasunaga, M.1
Masuda, N.2
Yagyu, M.3
Asai, M.4
Yamada, M.5
Masaki, A.6
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